Adom Library
Public Made by Adomby adom
adom-lbr — the EDA library translator. Bring a component in from any supported EDA tool and convert it to any other (KiCad ⇄ Altium ⇄ EAGLE/Fusion) through one canonical adom-lbr JSON — symbol + footprint + 3D + pin↔pad map. Altium is written natively (no Altium needed). Includes the adom-lbr Manager: browse wiki components and view symbol/footprint/3D + the per-EDA layer stackup.
Generated symbols mirror the PACKAGE (pins on 4 sides, rotated colliding names) - EEs expect two-column left/right symbols with logical grouping
From the fusion-bridge maintainer, relaying John's review of a generated symbol (2026-08-15, the ADS8588SIPM 64-pin ADC): "the pins on the symbol look awful and are not drawn the way a normal electrical engineer would draw them... any EE would be embarrassed by this."
Root cause, confirmed by inspecting the generated .lbr: the symbol generator lays pins out on ALL FOUR sides of the body (rot R0/R90/R180/R270), mirroring the physical package (LQFP-64 in this case). A schematic symbol is not a package drawing. The four-sided layout forces the top and bottom pin names to render rotated, colliding with the outline and the pin stubs, and scatters logically-related pins to physical corners.
What EE convention wants instead (and what we hand-fixed in fusion-bridge's bundled sample, screenshot-verified in Fusion):
- Two columns only: inputs/analog on the LEFT, outputs/bus/control on the RIGHT, power grouped (bottom-left or a separate power block). Every pin name horizontal.
- Logical grouping with a blank row between groups (e.g. AIN_nP/AIN_nGND pairs together, REF block together, the DB0-DB15 bus contiguous and in order, control signals clustered, supplies clustered).
- Body wide enough that the longest left + right names never approach each other (we used a 60mm body for 16-char names at 1.778mm text).
- 2.54mm pitch, pins length "middle", numbers outside, names inside - which the EAGLE defaults already do once the pins are on left/right.
The fix in the generator is mostly a layout-policy change: classify pins (in/out/bus/power/passive) from the datasheet data it already has, sort into left/right groups, and emit two columns. Bus detection (DBn, Dn, ADn) keeps buses contiguous. Happy to share the exact regrouping heuristics we used for the sample - they're ~40 lines of python in fusion-bridge's history (commit "v1.9.17").
This affects every symbol the pipeline generates, so a fix here upgrades every library at once.