Adom Library
Public Made by Adomby adom
adom-lbr — the EDA library translator. Bring a component in from any supported EDA tool and convert it to any other (KiCad ⇄ Altium ⇄ EAGLE/Fusion) through one canonical adom-lbr JSON — symbol + footprint + 3D + pin↔pad map. Altium is written natively (no Altium needed). Includes the adom-lbr Manager: browse wiki components and view symbol/footprint/3D + the per-EDA layer stackup.
pad-clearance rejects 559 of 1314 stock KiCad footprints (43%); 225 of them at exactly the 0.2mm threshold
adom-lbr validate's pad-clearance rule rejects 559 of 1,314 stock KiCad footprints (43%), including land patterns that are byte-identical to the ones KiCad ships. It is the top FAIL reason in the component-page factory, so it is silently costing us parts.
The boundary case is unambiguous
225 of the 559 fail at exactly 0.200 mm, which the rule's own message says should pass:
$ adom-lbr validate SOT-666.lbr
FAIL: [pad-clearance] copper closer than 0.2 mm: SOT-666 pads 1 and 2 are 0.200 mm apart
"closer than 0.2 mm" and "0.200 mm apart" cannot both be true. Looks like <= where < is meant, or a float compare without an epsilon. Fixing just this recovers 225 footprints with no judgement call required.
The threshold is also too strict for fine pitch
The remaining 334 sit below 0.2 mm — but so do the standard land patterns for every fine-pitch package. SOT-563 is the clearest example: our copy is byte-identical to Package_TO_SOT_SMD.pretty/SOT-563.kicad_mod, pads 0.675 x 0.35 mm on 0.5 mm pitch, so the gap is 0.15 mm by construction. There is no defect to find — 0.15 mm is simply what a 0.5 mm-pitch land pattern looks like.
Measured across the three libraries:
| library | failing | total | |
|---|---|---|---|
| Package_DFN_QFN | 482 | 776 | 62% |
| Package_SO | 66 | 401 | 16% |
| Package_TO_SOT_SMD | 11 | 137 | 8% |
Gap distribution of the failures:
225 at 0.200 mm <- boundary bug, should pass on the rule's own wording
125 at 0.150 mm <- standard 0.5 mm-pitch land pattern
114 at 0.125 mm
43 at 0.175 mm
19 at 0.100 mm
rest scattered 0.05-0.195
QFN/DFN taking 62% matters right now, given the pin-1 / QFN work that just landed — a rule that rejects most of the QFN library will fight it.
Why this is costing parts
factory.py gates on adom-lbr validate and logs FAIL: lbr invalid when it does not pass, which writes the slug into done.txt and permanently excludes it from the worklist. So every false positive here is a part quietly dropped from the 10k, not a part retried later. lbr invalid is currently the top failure mode across waves 9 and 10 (29 of them), and the one I traced end to end — RT6252BHGH6F, an RT6252 in SOT-563 — has a symbol and footprint that agree perfectly on all 6 pins. Nothing about it is wrong.
Suggested shape
- Fix the boundary so a gap of exactly the threshold passes. Recovers 225 outright.
- Scale the threshold to pitch rather than using a flat 0.2 mm — e.g. allow down to ~0.1 mm for pitches at or below 0.5 mm, since that is what IPC land patterns actually produce. Or demote sub-threshold clearance to a WARNING and keep it an error only where pads genuinely overlap (negative gap), which is the case the message describes: "A pad mapping that grows into its neighbour is a short." True overlap is a real defect; a 0.15 mm gap on a SOT-563 is not.
The overlap case is worth keeping as an error — that check caught a real one on ss41f, where a remap had grown pads into each other by 0.98 mm and 1.50 mm.
Reproduce
KL='/path/to/kicad/share/kicad/footprints'
adom-lbr generate --fp "$KL/Package_TO_SOT_SMD.pretty/SOT-563.kicad_mod" --output /tmp/t.lbr
adom-lbr validate /tmp/t.lbr # FAIL, pads 0.150 mm apart
adom-lbr generate --fp "$KL/Package_TO_SOT_SMD.pretty/SOT-666.kicad_mod" --output /tmp/b.lbr
adom-lbr validate /tmp/b.lbr # FAIL, pads 0.200 mm apart <- the boundary case
Found on adom-lbr 2.32.0.