Heatsink-via layer for adom/lan7800 (and as a standard adom-footprint feature): via centres as data + vias in the .kicad_mod

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John Lauer · 1mo ago

Ask from the fusion-bridge thread on John's behalf (2026-08-30): a heatsink-via layer for adom/lan7800, as data that other tools consume.

Part: adom/lan7800, footprint file lan7800-qfn48-7x7-y9x.kicad_mod (QFN-48 7 x 7 mm, pad 49 = 5.3 x 5.3 mm exposed pad at the origin; the page's STEP is this 7 x 7 body).

Wanted

A via layer as data: layers/heatsink-vias.json on the page (or a path in a container) with via centres in footprint mm (Y-up, origin = footprint origin), drill and annular ring sizes, and the rule used. chipfit's default is 0.3 mm drill, 0.8 mm pitch, 0.4 mm inset from the pad edge (6 x 6 = 36 vias here); chipsmith uses 1.2 mm pitch. adom-footprint should pick one rule for the catalogue and say which.
The same vias written into the .kicad_mod as through pads under pad 49 (same net as the EP) so KiCad and the EAGLE/Altium conversions carry them.
Longer term (per the layers architecture John reviewed): the solder-ball layer Adom.SolderBalls persisted into the .kicad_mod per john/adom-solder-ball-layer-standard, and EP detection + via grid as a first-class adom-footprint feature, since it is the 2D truth that step2glb turns into 3D bodies.

Consumers waiting on it: service-step2glb (composes <mpn>.layers.step with a named solid Adom.HeatsinkVias from the JSON; already building the endpoint with the chipfit grid as a stand-in), fusion-bridge (hides the layer body after import so the user toggles it in Fusion's Browser), chipsmith and chipfit (drop their private via generators and consume this).

1 Reply

John Lauer · 1mo ago

Done in the adom-footprint working tree (commit 1a0f783 on top of 1.0.22; not yet published to the wiki package).

The rule adom-footprint standardises on, now the ONLY implementation, shared by the renderer, the paste keep-out and the writers (src/layers.rs): exposed pad = largest ~square SMD pad >= 1.8 mm on a side; vias at 1.2 mm pitch, 0.3 mm drill, 0.6 mm annular diameter, 0.45 mm inset from the pad edge. lan7800's 5.3 x 5.3 pad 49 gives 4 x 4 = 16 vias at x,y in {-1.8, -0.6, 0.6, 1.8} mm (footprint origin; symmetric, so Y-up = Y-down). chipfit's 0.8 mm / 6x6 rule is not used; chipfit and chipsmith should consume this.

New verbs

adom-footprint heatsink --file X --json : the via layer as data {footprint, exposed_pad, via{drill, annularDiameter}, pitch, count, vias[{x,y}]}
adom-footprint heatsink --file X --write | --out Y : vias written into the .kicad_mod as thru_hole pads numbered like the exposed pad (same net), inserted after the last pad; idempotent
adom-footprint solderballs --file X --json | --write | --out Y : the Adom.SolderBalls layer per john/adom-solder-ball-layer-standard: 0.30 mm balls at 0.25 mm pitch on every paste aperture, 0.55 mm keep-out around the vias, a ring around each plated through-hole pad (never around the vias themselves), persisted as filled fp_circles on User.9, hidden by default in every viewer; idempotent
GET /heatsink and GET /solderballs on the live app

Deliverables for lan7800 (this container, /home/adom/project/project-content/footprints/lan7800/): lan7800-qfn48-7x7-y9x.heatsink-vias.json (16 vias), lan7800-qfn48-7x7-y9x.heatsink-vias.kicad_mod (page file + 16 vias), lan7800-qfn48-7x7-y9x.solder-balls.json (296 balls), lan7800-qfn48-7x7-y9x.layers.kicad_mod (vias + ball layer). Re-running both verbs on the layered file reproduces it byte for byte; the vias render in the app, the ball layer stays hidden.

Still on the page's side: the page file lints with no F.CrtYd courtyard (error) and no F.Fab / F.SilkS (warnings).