Adom Fields

@@ -112,3 +112,11 @@ Every DC net must converge before a summary is published, even when the thermal Plated through-hole pads (including circular and oblong KiCad drills) connect copper layers in both electrical and thermal models. They are counted separately as `platedPads`; routing-via counts retain their original meaning. Barrel conduction assumes 25 µm plating, not a measured fabrication result. Omitting these pad barrels can falsely isolate a connector pad even when native DRC reports full connectivity.  `dcMaxIterations` defaults to 6000 and can be explicitly increased up to 100000 for diagnostic convergence work. This does not change the acceptance tolerance. Reported solver residuals are recomputed from A*x-b, rather than trusting only the internal CG recurrence. Retain failed runs and compare mesh sensitivity; extra iterations cannot repair missing geometry or justify a power rating.++## Explicit pin currents (source candidate)++Each `loads.<net>` may supply `terminals`, an array of `{ "reference": "J1", "pad": "1", "amps": 3.0 }` rows. Positive current enters the board copper; negative current leaves it. Positive and negative totals must each equal that net's `amps`. Include sense-branch current separately instead of assigning the entire load to every narrow track. Pin identifiers must resolve uniquely on the specified net; duplicate, missing, wrong-net and unbalanced assignments are rejected. Pads omitted from this explicit boundary condition draw zero modeled current, so this is an engineering assumption to review against the circuit, including fixture return paths and auxiliary loads. Repeated pad numbers currently require a unique physical pad and are rejected when ambiguous.++Reports retain the declared pins in `terminalAssignments` and label every net as `explicit` or `heuristic`. Legacy loads without the array retain the existing terminal heuristic. A loaded net that cannot be solved now prevents publishing a partial result. No partial current injection is accepted if any nonzero terminal has no resolved copper.++This change does not replace the current injection's existing 1 mm neighborhood approximation with an exact package contact model. Refine the mesh and review pad geometry and boundary conditions before accepting density values. It also does not model the external MOSFET heatsink or certify thermal performance. This candidate is stacked on physical-stack PR #5; neither change is a deployed shared release yet.

@@ -104,3 +104,11 @@ Every DC net must converge before a summary is published, even when the thermal Plated through-hole pads (including circular and oblong KiCad drills) connect copper layers in both electrical and thermal models. They are counted separately as `platedPads`; routing-via counts retain their original meaning. Barrel conduction assumes 25 µm plating, not a measured fabrication result. Omitting these pad barrels can falsely isolate a connector pad even when native DRC reports full connectivity.  `dcMaxIterations` defaults to 6000 and can be explicitly increased up to 100000 for diagnostic convergence work. This does not change the acceptance tolerance. Reported solver residuals are recomputed from A*x-b, rather than trusting only the internal CG recurrence. Retain failed runs and compare mesh sensitivity; extra iterations cannot repair missing geometry or justify a power rating.++## Explicit pin currents (source candidate)++Each `loads.<net>` may supply `terminals`, an array of `{ "reference": "J1", "pad": "1", "amps": 3.0 }` rows. Positive current enters the board copper; negative current leaves it. Positive and negative totals must each equal that net's `amps`. Include sense-branch current separately instead of assigning the entire load to every narrow track. Pin identifiers must resolve uniquely on the specified net; duplicate, missing, wrong-net and unbalanced assignments are rejected. Pads omitted from this explicit boundary condition draw zero modeled current, so this is an engineering assumption to review against the circuit, including fixture return paths and auxiliary loads. Repeated pad numbers currently require a unique physical pad and are rejected when ambiguous.++Reports retain the declared pins in `terminalAssignments` and label every net as `explicit` or `heuristic`. Legacy loads without the array retain the existing terminal heuristic. A loaded net that cannot be solved now prevents publishing a partial result. No partial current injection is accepted if any nonzero terminal has no resolved copper.++This change does not replace the current injection's existing 1 mm neighborhood approximation with an exact package contact model. Refine the mesh and review pad geometry and boundary conditions before accepting density values. It also does not model the external MOSFET heatsink or certify thermal performance. This candidate is stacked on physical-stack PR #5; neither change is a deployed shared release yet.

@@ -1,5 +1,6 @@ //! adom-fields: where the current and the heat go on your board. use sha2::{Digest, Sha256};+mod terminals; mod eagle; mod parts; mod signals; mod heatsink; mod board; mod fields; mod raster; mod sexp; mod solve; mod tex; mod serve; mod vendor; use clap::{Parser, Subcommand}; use std::path::PathBuf;@@ -61,6 +62,7 @@ pub fn run_analyze(board: &str, spec_path: &str, out: &PathBuf, pitch: f64, neck     b.validate_layers()?;     fields::dielectric_mm(&spec, b.layer_names.len())?;     for (layer,t) in &spec.copperUmByLayer { if !b.layer_names.contains(layer) || !t.is_finite() || *t<=0.0 {return Err("copperUmByLayer requires actual board copper layers and positive thicknesses".into());} }+    for (net, load) in &spec.loads { if let Some(rows) = &load.terminals { terminals::resolve(&b, net, load.amps, rows)?; } }     let layers: Vec<&str> = b.layer_names.iter().map(String::as_str).collect();     spec.signals.validate_layers(&layers)?;     for hot in spec.hot.values() {if !hot.watts.is_finite() || hot.watts<0.0 {return Err("hot watts must be finite and nonnegative".into());}}@@ -84,6 +86,7 @@ pub fn run_analyze(board: &str, spec_path: &str, out: &PathBuf, pitch: f64, neck     let t0 = std::time::Instant::now();     let mut lines: Vec<String> = Vec::new();     let f = fields::analyze(&b, &spec, pitch, neck, &mut |s| { eprintln!("{s}"); lines.push(s.to_string()); });+    for (net, load) in &spec.loads { if load.amps > 0.0 && !f.nets.iter().any(|r| r.net == *net) { return Err(format!("{net}: loaded net was not solved; no partial report will be published")); } }     for net in &f.nets { fields::validate_current_residual(&net.net, net.residual)?; }     if !f.heat_residual.is_finite() || f.heat_residual>1e-6 || !f.heat_moving_residual.is_finite() || f.heat_moving_residual>1e-6 {return Err(format!("thermal solve did not converge: still {}, moving {}; refine the model or increase the solve budget",f.heat_residual,f.heat_moving_residual));}     let tex = out.join("tex");

@@ -0,0 +1,62 @@+//! Explicit signed pin currents. Positive enters copper; negative leaves it.+use crate::board::{Board, Pad};+use serde::{Deserialize, Serialize};+use std::collections::BTreeSet;++#[derive(Clone, Debug, Deserialize, Serialize)]+#[serde(deny_unknown_fields)]+pub struct Terminal {+    pub reference: String,+    pub pad: String,+    pub amps: f64,+}++pub fn resolve<'a>(board: &'a Board, net: &str, amps: f64, rows: &[Terminal])+    -> Result<Vec<(&'a Pad, f64)>, String>+{+    if rows.is_empty() { return Err(format!("{net}: explicit terminals must not be empty")); }+    let mut seen = BTreeSet::new();+    let mut result = Vec::new();+    let (mut positive, mut negative) = (0.0, 0.0);+    for t in rows {+        if !t.amps.is_finite() || !seen.insert((&t.reference, &t.pad)) {+            return Err(format!("{net}: terminal currents must be finite and pin assignments unique"));+        }+        let pads: Vec<_> = board.pads.iter().filter(|p| p.reference == t.reference && p.pad == t.pad).collect();+        if pads.len() != 1 || pads[0].net != net {+            return Err(format!("{net}: {}.{} must identify exactly one pad on this net", t.reference, t.pad));+        }+        positive += t.amps.max(0.0);+        negative += (-t.amps).max(0.0);+        result.push((pads[0], t.amps));+    }+    let tolerance = 1e-9_f64.max(amps.abs() * 1e-8);+    if !amps.is_finite() || amps < 0.0 || (positive - amps).abs() > tolerance || (negative - amps).abs() > tolerance {+        return Err(format!("{net}: sources ({positive} A) and sinks ({negative} A) must each equal load ({amps} A)"));+    }+    Ok(result)+}++#[cfg(test)]+mod tests {+    use super::*;+    fn board() -> Board {+        Board { pads: [("J1", "1", "V"), ("F1", "1", "V"), ("R1", "1", "V"), ("J2", "1", "GND")].into_iter().map(|(r,p,n)| Pad { reference:r.into(), pad:p.into(), net:n.into(), x:0., y:0., layers:vec!["F.Cu".into()], area:1. }).collect(), ..Board::default() }+    }+    fn row(reference: &str, amps: f64) -> Terminal { Terminal { reference:reference.into(), pad:"1".into(), amps } }+    #[test] fn main_and_sense_branches_preserve_assigned_currents() {+        let b=board();+        let r=resolve(&b,"V",3.,&[row("J1",3.),row("F1",-2.9999),row("R1",-0.0001)]).unwrap();+        assert_eq!(r[1].0.reference,"F1"); assert_eq!(r[2].1,-0.0001);+    }+    #[test] fn reject_wrong_net_missing_duplicate_and_unbalanced_terminals() {+        let b=board();+        for rows in [vec![],vec![row("J1",3.),row("J2",-3.)],vec![row("J1",3.),row("MISSING",-3.)],vec![row("J1",3.),row("F1",-2.)],vec![row("J1",3.),row("F1",-1.5),row("F1",-1.5)],vec![row("J1",f64::NAN),row("F1",-3.)]] {+            assert!(resolve(&b,"V",3.,&rows).is_err());+        }+    }+    #[test] fn reject_ambiguous_repeated_pad_number() {+        let mut b=board(); b.pads.push(b.pads[0].clone());+        assert!(resolve(&b,"V",3.,&[row("J1",3.),row("F1",-3.)]).is_err());+    }+}