Adom Fields
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Adom Fields: where the current and the heat go on your board.
Cross-section impedance ignores local reference copper when whole-layer plane classification is null
Adom Fields0.10.3; AIFlow0.2.30; KiCad10.0.6; Linux solver reading a Windows-native saved four-layer board. Local installed Fields source xsec.rs, review() selects reference planes from review.checks.stackup.layers[].plane. No installed runtime was changed.
Observed output: B.Cu cross-section rows report117.0ohm for0.2mm traces; a USB pair at0.2654mm width/0.205mm gap reports100.3ohm. The layer classifier names only In1.Cu as a plane; In2.Cu has plane:null and planeCover0.39. The review reports B.Cu planeMm1.14. However a native filled-polygon projection confirms the USB bottom-layer centerlines are covered by local In2 GND, apart from separately excluded connector/via antipads, only0.1835mm away. This is a model-reference mismatch, not proof of the pair's actual impedance or compliance.
Source observation: xs_for chooses the nearest layer for which the whole-layer plane classifier is non-null. It never inspects the local reference under a signal; the pair report omits the selected reference layer/distance. A valid local plane region is therefore silently ignored when its total layer coverage is insufficient. Width/gap recommendations based on that assumed distant plane can drive an unnecessary board edit. Other routes truly lack local GND and remain unresolved; this report is not a global waiver.
Generic reproduction to add: a four-layer board with the same B.Cu pair and a continuous In2 GND strip under the full pair, while varying unrelated In2 copper far away across the classifier threshold. The local cross-section should not jump merely because remote copper changes. Include a genuinely absent/broken-reference case, which must not get a passing ideal-plane result.
Requested change: report reference net/layer/distance and assumptions for each evaluated section, select/check reference locally or return unsupported/incomplete for mixed coverage, and avoid claiming one whole-net impedance from a representative cross-section. Keep native connectivity, return-path, transition and fabrication verification separate. No private CAD or screenshots attached, and no acceptance threshold was changed.