Closed bug report

0.2 mm grid joins same-net copper 0.14 mm apart: a false neck sets VTILE's peak (133.6 A/mm2) and hides the real one

Drew Owens · ·closed by John Lauer

adom-fields 0.10.2 · adom/core 4.15.3 · board saved by KiCad 10.0.7 (format 20260206) · --pitch 0.2 (default)

What I did: adom-fields analyze on a 4-layer board where each power net has track-following zones on F.Cu and B.Cu. Two separate VTILE zones on F.Cu end close together. KiCad keeps their fills 0.142 mm apart (measured on the saved filled_polygons with shapely), and the net's two sides are joined only through other layers.

What happened: the solve treats the two fills as joined. VTILE's peak landed in the gap, as a neck that does not exist:

VTILE  1.5 A  peakJ 133.6  at [117.9, 134.9] F.Cu
review.checks.ampacity: VTILE neck 0.32 mm at [117.9, 134.9], IPC 10C 1.05 A, solved rise 17.2 C

The J map shows a large share of VTILE's current running through that false shortcut. On the same board, two VSYS pieces were 0.081 mm and 0.291 mm apart (B.Cu and F.Cu) and were probably joined the same way, without setting VSYS's peak.

My reading: a cell counts as copper when its centre lies in copper, and neighbouring copper cells join. Same-net copper closer than about one cell then becomes one conductor. KiCad keeps no clearance between same-net zones, so this geometry is legal and easy to make. Because Fields reports one maximum per net, the false peak also hides the net's real one.

Expected: join copper only where the board joins it. For example, rasterize each filled polygon and track separately and connect cells across items only where the source geometry overlaps or touches. Or at least report "same-net copper closer than one cell was merged at (x, y)" as a finding, so the peak is not taken at face value.

Worked around by keeping separate same-net pieces on a layer at least 0.46 mm apart (more than two cells). I'll add the before and after peaks here when the new solve is done.

2 Replies

Drew Owens ·

adom-fields 0.10.2 · same spec, 0.2 mm grid · board saved and filled by KiCad 10.0.7

Before and after, on the same board:

VTILE peak where
Two VTILE pours 0.14 mm apart (KiCad's fill keeps them separate) 133.6 A/mm² the gap between them at (117.9, 134.9): no copper there
The same pours kept at least 0.46 mm apart 61.6 A/mm² a cluster of short track joints at (114.7, 132.9)

Every other net's peak is unchanged to the first decimal (VTILE_EDGE 106.4, VBUS_C 73.3, VBUS 57.4, VSYS 42.7, VBAT 39.0), which fits the grid bridging the narrow gap rather than anything about the copper itself.

The workaround on our side: the pour generator keeps separate pieces of one net at least 0.5 mm apart before KiCad fills them. A check in Fields for same-net copper closer than one cell (or a warning naming the spot) would have saved an hour of chasing a neck that was not on the board.

John Lauer ·

Fixed in adom-fields 0.10.3. Your reading was right, and the before and after numbers made it easy to confirm.

  • Pieces come from the geometry. Each net's copper on each layer is now split into its real pieces from the board's geometry: the fills, tracks, pads and via rings that actually touch or overlap.
  • Pieces don't conduct into each other. A solve cell belongs to the piece with the most copper in it, and cells of different pieces do not conduct. Two fills KiCad keeps 0.14 mm apart stay two conductors, joined only where the board joins them, through the other layers.
  • Every such spot is reported. Each place where two pieces came closer than a cell is listed in nets[].piecesKeptApart (layer and position) and in the log. Re-run at --pitch 0.1 if you want the copper there resolved exactly.

Test board: two V fills on F.Cu 0.14 mm apart, joined only through vias and a 0.3 mm bottom track.

  • 0.10.2 put the peak in the gap on F.Cu, which is exactly your VTILE case.
  • 0.10.3 sends the current through the vias and the bottom track, where the peak really is, and lists the 10 cells along the gap.

On four of our own boards every net's peak, copper and Joule loss is unchanged to within 0.3 %.

Update with adom-wiki pkg install adom/adom-fields (check adom-fields --version shows 0.10.3). Your 0.5 mm spacing in the pour generator is no longer needed for Fields' sake. On your board, VTILE should now report its real peak (your 61.6 A/mm² spot) without moving the pours.

John Lauer closed this ·

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