Adom Custom Electronic Load
Public Made by Adomby adom
Independent compact digitally controlled load design for 3rdPartyFab; research and AIFlow evidence in progress
10054d3
56m ago
R0 placement review
The latest kicad/placement-candidate.kicad_pcb contains all 102 components on the molecule board. Native KiCad reports zero DRC violations and 218 unconnected items in kicad/candidate-drc.json. This is a placement checkpoint, not a routed board or fabrication release.
The rejected first proposal remains documented in design/placement-check.log and design/placement-drc.json. Its MSOP spacing findings were resolved by using TI's manufacturer land pattern (1.45 x 0.30 mm pads), rather than suppressing copper-clearance checks. The GCT USB4105 land pattern was preserved; its manufacturer-defined locating-hole geometry now has a local 0.15 mm hole-clearance constraint, only between items belonging to J8. Nominal observed clearance is 0.1944 mm. This exceeds the selected profile's copper-spacing floor, but drill-process DFM must still be verified before fabrication; it is not a blanket board-wide relaxation.
Reference labels were repositioned using native text bounds against courtyard/pad/drill envelopes. U2 still lacks an accepted body-clear label location despite zero native DRC findings; fitted-model visibility and final two-sided labels remain open. DRC does not check all assembled label occlusion.
The MOSFET is horizontal tab-up for a top-side heatsink. The heatsink clamp, electrical insulation, contact resistance, PCB support, fan guard and duct remain mechanical design work. The proposed ATS heatsink is a candidate only, not a completed mounted thermal solution. Routing must accommodate the finalized mounting and cooling keepouts before release.
# R0 placement review
The latest `kicad/placement-candidate.kicad_pcb` contains all 102 components on the molecule board. Native KiCad reports **zero DRC violations and 218 unconnected items** in `kicad/candidate-drc.json`. This is a placement checkpoint, not a routed board or fabrication release.
The rejected first proposal remains documented in `design/placement-check.log` and `design/placement-drc.json`. Its MSOP spacing findings were resolved by using TI's manufacturer land pattern (1.45 x 0.30 mm pads), rather than suppressing copper-clearance checks. The GCT USB4105 land pattern was preserved; its manufacturer-defined locating-hole geometry now has a local 0.15 mm hole-clearance constraint, only between items belonging to J8. Nominal observed clearance is 0.1944 mm. This exceeds the selected profile's copper-spacing floor, but drill-process DFM must still be verified before fabrication; it is not a blanket board-wide relaxation.
Reference labels were repositioned using native text bounds against courtyard/pad/drill envelopes. U2 still lacks an accepted body-clear label location despite zero native DRC findings; fitted-model visibility and final two-sided labels remain open. DRC does not check all assembled label occlusion.
The MOSFET is horizontal tab-up for a top-side heatsink. The heatsink clamp, electrical insulation, contact resistance, PCB support, fan guard and duct remain mechanical design work. The proposed ATS heatsink is a candidate only, not a completed mounted thermal solution. Routing must accommodate the finalized mounting and cooling keepouts before release.