project
Adom Custom Electronic Load
Public Made by Adomby adom
Two-layer digitally controlled electronic-load prototype. Compact R11 is under active electrical, cooling and probe-access review; not a manufacturing release.
← Commit history
Preserve branch-current and auxiliary envelope results without closing live gates
7 files changed
+1458
design/aux-current-envelope/summary.jsonadded+196@@ -0,0 +1,196 @@+{+ "kind": "conditional-auxiliary-DC-envelope",+ "formalAcceptance": false,+ "boardSha256": "54f1aab0a34622d1c3675c13f4aeb7a678b0cee8b5a4d3bfd7484b10edb8dcf6",+ "solverSha256": "8e65c1a70aa498b7b045caa4309be3588dcdba4f3aca09361e241d990c5329d2",+ "source": "J3.1",+ "totalAmps": 0.3,+ "cases": [+ {+ "sink": "J9.1",+ "inputIdentity": {+ "algorithm": "sha256",+ "board": "54f1aab0a34622d1c3675c13f4aeb7a678b0cee8b5a4d3bfd7484b10edb8dcf6",+ "solverVersion": "0.6.2",+ "spec": "438fa8b3caf16c3676b169f6c55b8c4ff99f92276e2307ff1cf5296a14c7f2d2"+ },+ "result": {+ "amps": 0.3,+ "copperMm2": 66.6,+ "iterations": 755,+ "jouleW": 0.004,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "5V_AUX",+ "peakAt": [+ 144.1,+ 90.3+ ],+ "peakJ": 21.8,+ "peakLayer": "F.Cu",+ "platedPads": 2,+ "residual": 6.568587319580788e-08,+ "vias": 7+ },+ "issues": []+ },+ {+ "sink": "U9.1",+ "inputIdentity": {+ "algorithm": "sha256",+ "board": "54f1aab0a34622d1c3675c13f4aeb7a678b0cee8b5a4d3bfd7484b10edb8dcf6",+ "solverVersion": "0.6.2",+ "spec": "a1abf428008ef48bc3d62d998ed0d5a1fb5d5be36c649fccc3eab972d22fcb4a"+ },+ "result": {+ "amps": 0.3,+ "copperMm2": 66.6,+ "iterations": 752,+ "jouleW": 0.006,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "5V_AUX",+ "peakAt": [+ 147.7,+ 64.3+ ],+ "peakJ": 22.7,+ "peakLayer": "B.Cu",+ "platedPads": 2,+ "residual": 8.049544593494674e-08,+ "vias": 7+ },+ "issues": []+ },+ {+ "sink": "U9.3",+ "inputIdentity": {+ "algorithm": "sha256",+ "board": "54f1aab0a34622d1c3675c13f4aeb7a678b0cee8b5a4d3bfd7484b10edb8dcf6",+ "solverVersion": "0.6.2",+ "spec": "01bf226c1d63b49336f64da6209030f43dcc25ed0e0f6edc1f6e8da3fc544713"+ },+ "result": {+ "amps": 0.3,+ "copperMm2": 66.6,+ "iterations": 752,+ "jouleW": 0.006,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "5V_AUX",+ "peakAt": [+ 147.7,+ 66.9+ ],+ "peakJ": 24.2,+ "peakLayer": "F.Cu",+ "platedPads": 2,+ "residual": 9.862565735336203e-08,+ "vias": 7+ },+ "issues": []+ },+ {+ "sink": "U5.4",+ "inputIdentity": {+ "algorithm": "sha256",+ "board": "54f1aab0a34622d1c3675c13f4aeb7a678b0cee8b5a4d3bfd7484b10edb8dcf6",+ "solverVersion": "0.6.2",+ "spec": "07905413ec552faf80936da82abc8e23ea4cbdec4f1fbac8cefa725e53c99546"+ },+ "result": {+ "amps": 0.3,+ "copperMm2": 66.6,+ "iterations": 750,+ "jouleW": 0.002,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "5V_AUX",+ "peakAt": [+ 122.1,+ 97.89999999999999+ ],+ "peakJ": 21.6,+ "peakLayer": "B.Cu",+ "platedPads": 2,+ "residual": 9.380233036328345e-08,+ "vias": 7+ },+ "issues": []+ },+ {+ "sink": "U5.5",+ "inputIdentity": {+ "algorithm": "sha256",+ "board": "54f1aab0a34622d1c3675c13f4aeb7a678b0cee8b5a4d3bfd7484b10edb8dcf6",+ "solverVersion": "0.6.2",+ "spec": "1380aff2ff4505e0177c1f4377ba23b66f77257d58b65194deec9886d32ba735"+ },+ "result": {+ "amps": 0.3,+ "copperMm2": 66.6,+ "iterations": 753,+ "jouleW": 0.002,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "5V_AUX",+ "peakAt": [+ 122.1,+ 97.89999999999999+ ],+ "peakJ": 21.6,+ "peakLayer": "B.Cu",+ "platedPads": 2,+ "residual": 8.965428335211985e-08,+ "vias": 7+ },+ "issues": []+ },+ {+ "sink": "L1.1",+ "inputIdentity": {+ "algorithm": "sha256",+ "board": "54f1aab0a34622d1c3675c13f4aeb7a678b0cee8b5a4d3bfd7484b10edb8dcf6",+ "solverVersion": "0.6.2",+ "spec": "6b3ebf3bca6de9f4b3f8bb52e6dcb0a70a21dd0d96444f23906d3cd5f5bffbff"+ },+ "result": {+ "amps": 0.3,+ "copperMm2": 66.6,+ "iterations": 751,+ "jouleW": 0.002,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "5V_AUX",+ "peakAt": [+ 122.1,+ 97.89999999999999+ ],+ "peakJ": 21.6,+ "peakLayer": "B.Cu",+ "platedPads": 2,+ "residual": 9.34937202303486e-08,+ "vias": 7+ },+ "issues": []+ }+ ],+ "limits": [+ "Assumes J3.1 is sole 5 V source and total continuous current <= 0.3 A; budget must be validated separately",+ "One consumer pin gets the entire current in each case; linear DC combinations are bounded by these cases at fixed conductivity",+ "Capacitor startup and boost switching pulses excluded; this is not a transient or thermal acceptance",+ "No heat-source or external heatsink qualification; fixed nominal copper and plating"+ ]+}
design/spec-branch-screen-diagnostic.jsonadded+438@@ -0,0 +1,438 @@+{+ "board": "Adom electronic load R0, 64 x 72 mm, 2 layers; engineering prototype",+ "copperUm": 35,+ "clearance": 0.2,+ "edgeClearance": 0.2,+ "fixedRefs": [+ "MP1",+ "MP2",+ "MP3",+ "MP4",+ "J1",+ "J2",+ "J3",+ "J4",+ "J5",+ "J6",+ "J7"+ ],+ "wideNets": {+ "DUT_POS": [+ 2.0,+ 1.5,+ 1.2+ ],+ "DUT_FUSED": [+ 2.0,+ 1.5,+ 1.2+ ],+ "LOAD_POS": [+ 2.0,+ 1.5,+ 1.2+ ],+ "SHUNT_P": [+ 2.0,+ 1.5,+ 1.2+ ],+ "GND": [+ 2.0,+ 1.5,+ 1.2+ ]+ },+ "midNets": {+ "5V_AUX": [+ 0.5,+ 0.4+ ],+ "V_GATE": [+ 0.3,+ 0.25+ ]+ },+ "kelvin": {+ "U4.10": "RSH1.2",+ "U4.9": "RSH1.3"+ },+ "chains": [+ {+ "refs": [+ "R8",+ "R9",+ "R10"+ ],+ "direction": "down"+ },+ {+ "refs": [+ "R18",+ "R19"+ ],+ "direction": "down"+ },+ {+ "refs": [+ "R22",+ "R23"+ ],+ "direction": "down"+ },+ {+ "refs": [+ "R27",+ "R28"+ ],+ "direction": "down"+ },+ {+ "refs": [+ "R35",+ "R36",+ "R37"+ ],+ "direction": "down"+ }+ ],+ "loads": {+ "DUT_POS": {+ "amps": 3.000220385674931,+ "maxRiseC": 10,+ "terminals": [+ {+ "reference": "J1",+ "pad": "1",+ "amps": 3.000220385674931+ },+ {+ "reference": "F1",+ "pad": "1",+ "amps": -3+ },+ {+ "reference": "R24",+ "pad": "1",+ "amps": -0.00022038567493112948+ },+ {+ "reference": "TP1",+ "pad": "1",+ "amps": 0+ }+ ],+ "currentModel": "resistive-branches"+ },+ "DUT_FUSED": {+ "amps": 3,+ "maxRiseC": 10,+ "terminals": [+ {+ "reference": "F1",+ "pad": "2",+ "amps": 3+ },+ {+ "reference": "D1",+ "pad": "2",+ "amps": -3+ }+ ],+ "currentModel": "resistive-branches"+ },+ "LOAD_POS": {+ "amps": 3.0000289156626505,+ "maxRiseC": 10,+ "terminals": [+ {+ "reference": "D1",+ "pad": "1",+ "amps": 3.0000289156626505+ },+ {+ "reference": "Q1",+ "pad": "2",+ "amps": -3+ },+ {+ "reference": "U4",+ "pad": "8",+ "amps": -2.891566265060241e-05+ }+ ]+ },+ "SHUNT_P": {+ "amps": 3,+ "maxRiseC": 10,+ "terminals": [+ {+ "reference": "Q1",+ "pad": "3",+ "amps": 3+ },+ {+ "reference": "RSH1",+ "pad": "1",+ "amps": -3+ }+ ]+ },+ "GND": {+ "amps": 3,+ "maxRiseC": 10,+ "terminals": [+ {+ "reference": "RSH1",+ "pad": "4",+ "amps": 3+ },+ {+ "reference": "J2",+ "pad": "1",+ "amps": -3+ }+ ]+ },+ "5V_AUX": {+ "amps": 0.3,+ "maxRiseC": 10+ }+ },+ "hot": {+ "Q1": {+ "watts": 5,+ "tabNet": "LOAD_POS",+ "maxRiseC": 15,+ "note": "Compact R0 5 W prototype target; 55 C case trip at assumed 40 C ambient unchanged. External heatsink remains required and unresolved; board-only solver is not cooling qualification."+ },+ "D1": {+ "watts": 1.65,+ "tabNet": "LOAD_POS"+ },+ "RSH1": {+ "watts": 0.18,+ "tabNet": "SHUNT_P"+ }+ },+ "hotMaxRiseC": 35,+ "pours": [+ {+ "net": "GND",+ "layers": [+ "B.Cu"+ ],+ "priority": 0,+ "connection": "solid",+ "name": "Power return and signal reference",+ "polygon": [+ [+ 98.3,+ 30.3+ ],+ [+ 161.7,+ 30.3+ ],+ [+ 161.7,+ 101.7+ ],+ [+ 98.3,+ 101.7+ ]+ ]+ },+ {+ "net": "GND",+ "layers": [+ "F.Cu"+ ],+ "priority": 0,+ "connection": "solid",+ "name": "Top return and shield",+ "polygon": [+ [+ 98.3,+ 30.3+ ],+ [+ 161.7,+ 30.3+ ],+ [+ 161.7,+ 101.7+ ],+ [+ 98.3,+ 101.7+ ]+ ]+ },+ {+ "name": "D1 heat spread front",+ "net": "LOAD_POS",+ "layers": [+ "F.Cu"+ ],+ "polygon": [+ [+ 106.5,+ 87.5+ ],+ [+ 114.5,+ 87.5+ ],+ [+ 114.5,+ 95+ ],+ [+ 106.5,+ 95+ ]+ ],+ "priority": 3,+ "connection": "solid",+ "clearance": 0.2,+ "minThickness": 0.25+ },+ {+ "name": "D1 heat spread back",+ "net": "LOAD_POS",+ "layers": [+ "B.Cu"+ ],+ "polygon": [+ [+ 106.5,+ 87.5+ ],+ [+ 114.5,+ 87.5+ ],+ [+ 114.5,+ 95+ ],+ [+ 106.5,+ 95+ ]+ ],+ "priority": 3,+ "connection": "solid",+ "clearance": 0.2,+ "minThickness": 0.25+ },+ {+ "name": "Shunt positive spread front",+ "net": "SHUNT_P",+ "layers": [+ "F.Cu"+ ],+ "polygon": [+ [+ 134.5,+ 84.7+ ],+ [+ 138,+ 84.7+ ],+ [+ 138,+ 88+ ],+ [+ 134.5,+ 88+ ]+ ],+ "priority": 3,+ "connection": "solid",+ "clearance": 0.2,+ "minThickness": 0.25+ },+ {+ "name": "Shunt positive spread back",+ "net": "SHUNT_P",+ "layers": [+ "B.Cu"+ ],+ "polygon": [+ [+ 134.5,+ 84.7+ ],+ [+ 138,+ 84.7+ ],+ [+ 138,+ 88+ ],+ [+ 134.5,+ 88+ ]+ ],+ "priority": 3,+ "connection": "solid",+ "clearance": 0.2,+ "minThickness": 0.25+ }+ ],+ "notPoured": [+ "BOOST_SW",+ "SERVO_FB",+ "SHUNT_P_SENSE",+ "SHUNT_N_SENSE",+ "I_SET",+ "DAC_OUT",+ "SET_DIV"+ ],+ "fab": {+ "rules": "fab",+ "target": "fab"+ },+ "sourcing": {+ "profile": "fab"+ },+ "molecule": {+ "pin": "medium",+ "gridMm": 2,+ "edgeMarginMm": 2,+ "cornerPinsNet": "GND"+ },+ "requireEvidence": [+ "calcs",+ "simulation"+ ],+ "qualificationNote": "Simultaneous 5 W/24 V/3 A limits; 3 A conductor, diode and shunt screens retained conservatively although initial DUT is 5 V/1 A. 25 W is a future option, not R0 rating. Actual cooling, USB and contact ratings remain unverified.",+ "planes": {+ "GND": "B.Cu"+ },+ "netClearance": {+ "USB_VBUS": 0.27+ },+ "stackupMm": [+ 1.53+ ],+ "dcMaxIterations": 60000,+ "diagnosticNote": "Explicit main-path diagnostic. Sense branches and alternate fixture returns are omitted boundary conditions; 5V_AUX retains heuristic allocation. Hot-part inputs preserved, but external Q1 heatsink absent. Not formal current/thermal acceptance.",+ "branchAssumptions": {+ "DUT_POS": "24 V across a 100k/10k series divider, both -1 percent; full 3 A F1 path retained. ADC input leakage is not included.",+ "LOAD_POS": "INA226 VBUS nominal 830 kohm (typical, no max specified here) gives 28.916 uA at 24 V. Nominal-only boundary, not guaranteed maximum."+ },+ "branchCurrentModel": {+ "boardThicknessMm": 1.6,+ "barrelPlatingUm": 25,+ "maxBarrelDensityAperMm2": 60+ }+}
design/step12-resistive-branch-summary.jsonadded+455@@ -0,0 +1,455 @@+{+ "formalAcceptance": false,+ "kind": "resistive-centerline-branch-diagnostic",+ "boardSha256": "54f1aab0a34622d1c3675c13f4aeb7a678b0cee8b5a4d3bfd7484b10edb8dcf6",+ "cases": [+ {+ "net": "DUT_POS",+ "sourceLayer": "F.Cu",+ "kclMaxResidualA": 8.881784197001252e-16,+ "conductors": [+ {+ "kind": "track",+ "id": "059ce1a7-f433-469d-9b6a-678dc218a59a",+ "widthMm": 1.5,+ "lengthMm": 4.242640687119285,+ "layer": "F.Cu",+ "amps": 2.0324422821776933,+ "resistanceOhm": 0.001393313854554773,+ "ipc2221RiseC": 3.542018776334623+ },+ {+ "kind": "track",+ "id": "1ec11d4d-a7f8-43ba-89f2-d39a2f8a9acd",+ "widthMm": 2.0,+ "lengthMm": 0.09999999999999432,+ "layer": "F.Cu",+ "amps": 0.0,+ "resistanceOhm": 2.463054187191978e-05,+ "ipc2221RiseC": 0.0+ },+ {+ "kind": "track",+ "id": "48579b3f-e2dd-4637-995b-aa820c60d63a",+ "widthMm": 1.2,+ "lengthMm": 0.4000000000000057,+ "layer": "F.Cu",+ "amps": 0.0,+ "resistanceOhm": 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"1ec11d4d-a7f8-43ba-89f2-d39a2f8a9acd",+ "widthMm": 2.0,+ "lengthMm": 0.09999999999999432,+ "layer": "F.Cu",+ "amps": 0.0,+ "resistanceOhm": 2.463054187191978e-05,+ "ipc2221RiseC": 0.0+ },+ {+ "kind": "track",+ "id": "48579b3f-e2dd-4637-995b-aa820c60d63a",+ "widthMm": 1.2,+ "lengthMm": 0.4000000000000057,+ "layer": "F.Cu",+ "amps": 0.0,+ "resistanceOhm": 0.00016420361247947686,+ "ipc2221RiseC": 0.0+ },+ {+ "kind": "track",+ "id": "5d038e37-16a5-4439-93bc-c47cd1387e2f",+ "widthMm": 1.2,+ "lengthMm": 6.799999999999997,+ "layer": "F.Cu",+ "amps": 3.1071958731466943e-16,+ "resistanceOhm": 0.0027914614121510657,+ "ipc2221RiseC": 5.811309045266356e-36+ },+ {+ "kind": "track",+ "id": "60f390a3-a7ec-4e47-b15c-2d723e4340d1",+ "widthMm": 2.0,+ "lengthMm": 3.394112549695436,+ "layer": "F.Cu",+ "amps": 2.593821363222702e-16,+ "resistanceOhm": 0.0008359883127328659,+ "ipc2221RiseC": 1.6614259518361342e-36+ },+ {+ "kind": "track",+ "id": "d786bd41-f974-4b16-8999-2072970ef7f1",+ "widthMm": 1.2,+ "lengthMm": 1.8439088914585837,+ "layer": "F.Cu",+ "amps": 1.1158799659740835,+ "resistanceOhm": 0.0007569412526513068,+ "ipc2221RiseC": 1.3095203906029125+ },+ {+ "kind": "track",+ "id": "da79ab43-5f04-49aa-ad8d-811344153464",+ "widthMm": 2.0,+ "lengthMm": 5.900000000000006,+ "layer": "F.Cu",+ "amps": 1.8841200340259163,+ "resistanceOhm": 0.001453201970443351,+ "ipc2221RiseC": 1.8560566510348602+ },+ {+ "kind": "track",+ "id": "e7e0648d-bb66-44b1-a6d1-e39f973cee68",+ "widthMm": 0.25,+ "lengthMm": 1.789999999999992,+ "layer": "F.Cu",+ "amps": 0.00022038567493114553,+ "resistanceOhm": 0.0035270935960590973,+ "ipc2221RiseC": 6.613686124181577e-08+ },+ {+ "kind": "track",+ "id": "f2fc3fc4-96a4-44d9-b1d6-088f689107ef",+ "widthMm": 1.5,+ "lengthMm": 1.9798989873223312,+ "layer": "F.Cu",+ "amps": 3.334913181286342e-16,+ "resistanceOhm": 0.0006502131321255602,+ "ipc2221RiseC": 4.724997314569972e-36+ },+ {+ "kind": "track",+ "id": "29268a34-4259-4166-9e37-23ddb102c3e2",+ "widthMm": 0.25,+ "lengthMm": 1.4142135623730951,+ "layer": "B.Cu",+ "amps": 0.000220385674931278,+ "resistanceOhm": 0.002786627709109547,+ "ipc2221RiseC": 6.613686124190612e-08+ },+ {+ "kind": "track",+ "id": "32e4be40-c3b7-4165-a9e0-c3e15841ff19",+ "widthMm": 0.25,+ "lengthMm": 5.656854249492381,+ "layer": "B.Cu",+ "amps": 0.00022038567493120017,+ "resistanceOhm": 0.011146510836438188,+ "ipc2221RiseC": 6.613686124185303e-08+ },+ {+ "kind": "track",+ "id": "4275237c-6f2e-45dd-9275-874e9854fe26",+ "widthMm": 0.25,+ "lengthMm": 31.5,+ "layer": "B.Cu",+ "amps": 0.00022038567493128328,+ "resistanceOhm": 0.06206896551724137,+ "ipc2221RiseC": 6.613686124190972e-08+ },+ {+ "kind": "track",+ "id": "6345ced8-02e7-45cd-8564-ec9c48bb761d",+ "widthMm": 1.5,+ "lengthMm": 5.656854249492381,+ "layer": "B.Cu",+ "amps": 1.1158799659740828,+ "resistanceOhm": 0.0018577518060730312,+ "ipc2221RiseC": 0.9066318959957518+ },+ {+ "kind": "track",+ "id": "985c76bc-62d5-4310-8410-741584ecc6a3",+ "widthMm": 1.5,+ "lengthMm": 6.400000000000006,+ "layer": "B.Cu",+ "amps": 1.1158799659740826,+ "resistanceOhm": 0.002101806239737276,+ "ipc2221RiseC": 0.9066318959957513+ },+ {+ "kind": "track",+ "id": "b14bc01b-8a70-4923-9ea7-6ba3ea89e105",+ "widthMm": 0.25,+ "lengthMm": 13.0,+ "layer": "B.Cu",+ "amps": 0.00022038567493141655,+ "resistanceOhm": 0.025615763546798027,+ "ipc2221RiseC": 6.613686124200063e-08+ },+ {+ "kind": "via",+ "id": "56b1fb26-65cb-4ff8-a01c-13b729bc64cb",+ "barrelAreaMm2": 0.03337942194439154,+ "amps": 1.1158799659740837,+ "resistanceOhm": 0.0008264435178808363+ },+ {+ "kind": "via",+ "id": "74242bdf-d456-477f-a551-d962cb8616bd",+ "barrelAreaMm2": 0.02552544031041706,+ "amps": 0.00022038567493168592,+ "resistanceOhm": 0.0010807338310749397+ },+ {+ "kind": "plated-pad",+ "pin": "J1.1",+ "barrelAreaMm2": 0.0632245521534946,+ "amps": 1.8841200340259157,+ "resistanceOhm": 0.00043632111192466483+ }+ ],+ "peakTrackRiseC": 2.981646765437912+ },+ {+ "net": "DUT_FUSED",+ "sourceLayer": "F.Cu",+ "kclMaxResidualA": 1.7763568394002505e-15,+ "conductors": [+ {+ "kind": "track",+ "id": "29677628-bdf8-4692-bd50-e61f84fe60af",+ "widthMm": 1.2,+ "lengthMm": 2.3499999999999943,+ "layer": "F.Cu",+ "amps": 0.3781971642197238,+ "resistanceOhm": 0.0009646962233169104,+ "ipc2221RiseC": 0.11198491115329694+ },+ {+ "kind": "track",+ "id": "61e46a9d-35eb-4259-8a82-3181679fd0c6",+ "widthMm": 1.2,+ "lengthMm": 1.7000000000000028,+ "layer": "F.Cu",+ "amps": 0.37819716421972355,+ "resistanceOhm": 0.0006978653530377678,+ "ipc2221RiseC": 0.11198491115329674+ },+ {+ "kind": "track",+ "id": "7a2a7149-89b7-4710-b2dc-7a4f4e5789a1",+ "widthMm": 1.2,+ "lengthMm": 0.9899494936611706,+ "layer": "F.Cu",+ "amps": 0.3781971642197238,+ "resistanceOhm": 0.00040638320757847715,+ "ipc2221RiseC": 0.11198491115329694+ },+ {+ "kind": "track",+ "id": "c98a8edc-8857-4314-bd0c-e61288bf0fe8",+ "widthMm": 2.0,+ "lengthMm": 2.799999999999997,+ "layer": "F.Cu",+ "amps": 2.621802835780276,+ "resistanceOhm": 0.0006896551724137923,+ "ipc2221RiseC": 3.932857269941616+ },+ {+ "kind": "track",+ "id": "03fb37ec-2541-4f2b-bd0e-451b85872ea7",+ "widthMm": 1.0,+ "lengthMm": 2.0999999999999943,+ "layer": "B.Cu",+ "amps": 0.3781971642197229,+ "resistanceOhm": 0.0010344827586206866,+ "ipc2221RiseC": 0.1512267463437164+ },+ {+ "kind": "track",+ "id": "172c1caa-d17d-4431-a38e-36419c474971",+ "widthMm": 1.0,+ "lengthMm": 0.05000000000001137,+ "layer": "B.Cu",+ "amps": 0.3781971642197242,+ "resistanceOhm": 2.463054187192678e-05,+ "ipc2221RiseC": 0.15122674634371763+ },+ {+ "kind": "via",+ "id": "18ce82ec-dc86-4449-8f2b-73b84a2039d1",+ "barrelAreaMm2": 0.03337942194439154,+ "amps": 0.3781971642197237,+ "resistanceOhm": 0.0008264435178808363+ },+ {+ "kind": "via",+ "id": "b20bb50a-e237-4200-b19c-efbe03811595",+ "barrelAreaMm2": 0.03337942194439154,+ "amps": 0.3781971642197239,+ "resistanceOhm": 0.0008264435178808363+ }+ ],+ "peakTrackRiseC": 3.932857269941616+ }+ ],+ "limits": [+ "Tracks modeled as uniform straight resistors; no filled polygon current distribution",+ "Pad central regions treated equipotential; pad necks/contact spreading not qualified",+ "35 um copper, 25 um barrel plating, 1.6 mm barrels assumed, not measured",+ "Both J1 source-layer extremes checked; actual contact distribution unknown",+ "No thermal coupling, conductivity-temperature feedback or pulse heating",+ "This diagnostic does not override AIFlow or Fields gates"+ ]+}
design/step12-sense-branch-summary.jsonadded+268@@ -0,0 +1,268 @@+{+ "kind": "sense-branch-diagnostic",+ "formalAcceptance": false,+ "inputIdentity": {+ "algorithm": "sha256",+ "board": "54f1aab0a34622d1c3675c13f4aeb7a678b0cee8b5a4d3bfd7484b10edb8dcf6",+ "solverVersion": "0.6.2",+ "spec": "f86b5b801d16c4e0224adec612e74405ee07702a541d7782ad748a6ef5cf84de"+ },+ "terminalAssignments": {+ "5V_AUX": {+ "mode": "heuristic",+ "pins": null+ },+ "DUT_FUSED": {+ "mode": "explicit",+ "pins": [+ {+ "amps": 3.0,+ "pad": "2",+ "reference": "F1"+ },+ {+ "amps": -3.0,+ "pad": "2",+ "reference": "D1"+ }+ ]+ },+ "DUT_POS": {+ "mode": "explicit",+ "pins": [+ {+ "amps": 3.000220385674931,+ "pad": "1",+ "reference": "J1"+ },+ {+ "amps": -3.0,+ "pad": "1",+ "reference": "F1"+ },+ {+ "amps": -0.00022038567493112948,+ "pad": "1",+ "reference": "R24"+ }+ ]+ },+ "GND": {+ "mode": "explicit",+ "pins": [+ {+ "amps": 3.0,+ "pad": "4",+ "reference": "RSH1"+ },+ {+ "amps": -3.0,+ "pad": "1",+ "reference": "J2"+ }+ ]+ },+ "LOAD_POS": {+ "mode": "explicit",+ "pins": [+ {+ "amps": 3.0000289156626505,+ "pad": "1",+ "reference": "D1"+ },+ {+ "amps": -3.0,+ "pad": "2",+ "reference": "Q1"+ },+ {+ "amps": -2.891566265060241e-05,+ "pad": "8",+ "reference": "U4"+ }+ ]+ },+ "SHUNT_P": {+ "mode": "explicit",+ "pins": [+ {+ "amps": 3.0,+ "pad": "3",+ "reference": "Q1"+ },+ {+ "amps": -3.0,+ "pad": "1",+ "reference": "RSH1"+ }+ ]+ }+ },+ "nets": [+ {+ "amps": 3.000220385674931,+ "copperMm2": 71.8,+ "iterations": 647,+ "jouleW": 0.014,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "DUT_POS",+ "peakAt": [+ 106.89999999999999,+ 93.69999999999999+ ],+ "peakJ": 42.7,+ "peakLayer": "F.Cu",+ "platedPads": 1,+ "residual": 8.537579182423423e-08,+ "vias": 2+ },+ {+ "amps": 3.0000289156626505,+ "copperMm2": 159.2,+ "iterations": 733,+ "jouleW": 0.027,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "LOAD_POS",+ "peakAt": [+ 126.89999999999999,+ 83.1+ ],+ "peakJ": 47.8,+ "peakLayer": "F.Cu",+ "platedPads": 1,+ "residual": 9.802374552737071e-08,+ "vias": 15+ },+ {+ "amps": 3.0,+ "copperMm2": 46.6,+ "iterations": 254,+ "jouleW": 0.026,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "SHUNT_P",+ "peakAt": [+ 126.89999999999999,+ 83.3+ ],+ "peakJ": 57.9,+ "peakLayer": "B.Cu",+ "platedPads": 1,+ "residual": 9.920461353185108e-08,+ "vias": 7+ },+ {+ "amps": 3.0,+ "copperMm2": 5211.5,+ "iterations": 7021,+ "jouleW": 0.053,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "GND",+ "peakAt": [+ 138.29999999999998,+ 92.5+ ],+ "peakJ": 42.7,+ "peakLayer": "F.Cu",+ "platedPads": 14,+ "residual": 9.83067050263189e-08,+ "vias": 48+ },+ {+ "amps": 3.0,+ "copperMm2": 19.7,+ "iterations": 147,+ "jouleW": 0.003,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "DUT_FUSED",+ "peakAt": [+ 108.89999999999999,+ 91.9+ ],+ "peakJ": 42.3,+ "peakLayer": "F.Cu",+ "platedPads": 0,+ "residual": 7.208780991872171e-08,+ "vias": 2+ },+ {+ "amps": 0.3,+ "copperMm2": 66.6,+ "iterations": 756,+ "jouleW": 0.001,+ "layers": [+ "F.Cu",+ "B.Cu"+ ],+ "net": "5V_AUX",+ "peakAt": [+ 153.9,+ 88.3+ ],+ "peakJ": 10.9,+ "peakLayer": "F.Cu",+ "platedPads": 2,+ "residual": 8.34572086330967e-08,+ "vias": 7+ }+ ],+ "issues": [+ {+ "at": [+ 117.4,+ 91.0+ ],+ "fix": "More copper under the tab and more vias to the other layers, or a heatsink; moving air alone does not bring it in.",+ "kind": "tab-rise",+ "layer": "F.Cu",+ "net": "LOAD_POS",+ "reference": "D1",+ "severity": "high",+ "what": "D1: +217 \u00b0C at its tab in still air (+138 \u00b0C in moving air) against a 35 \u00b0C budget"+ },+ {+ "at": [+ 127.46,+ 82.0+ ],+ "fix": "More copper under the tab and more vias to the other layers, or a heatsink; moving air alone does not bring it in.",+ "kind": "tab-rise",+ "layer": "F.Cu",+ "net": "LOAD_POS",+ "reference": "Q1",+ "severity": "high",+ "what": "Q1: +469 \u00b0C at its tab in still air (+389 \u00b0C in moving air) against a 35 \u00b0C budget"+ },+ {+ "at": [+ 136.625,+ 85.7+ ],+ "fix": "More copper under the tab and more vias to the other layers, or a heatsink; moving air alone does not bring it in.",+ "kind": "tab-rise",+ "layer": "F.Cu",+ "net": "SHUNT_P",+ "reference": "RSH1",+ "severity": "high",+ "what": "RSH1: +163 \u00b0C at its tab in still air (+93 \u00b0C in moving air) against a 35 \u00b0C budget"+ }+ ],+ "limitations": {+ "DUT_POS": "24 V across a 100k/10k series divider, both -1 percent; full 3 A F1 path retained. ADC input leakage is not included.",+ "LOAD_POS": "INA226 VBUS nominal 830 kohm (typical, no max specified here) gives 28.916 uA at 24 V. Nominal-only boundary, not guaranteed maximum."+ }+}
docs/completion-plan.md+2@@ -1,3 +1,5 @@+Latest 10 October work: explicit-terminal Fields source PR 6 (stacked on PR 5) is open, with 25 tests and source/diagnostic evidence. Sense-branch and auxiliary sweeps completed; an independent resistor model and an isolated AIFlow Rust candidate agree on the two misleading width failures. The candidate passed current in an isolated run under stated assumptions; live acceptance remains unchanged. See explicit-terminal-analysis.md. One 45-second Fields walkthrough was decoded/reviewed, bringing the raw inventory to 68. The dashboard now shows the saved board-19 diagnostic, not the old board-17 screenshot. Continue current-gate integration and physical cooling; do not stop at the source update.+ # Active completion contract Current-step gate is explicitly failed: its width-only heuristic flags DUT_POS 0.25 mm and DUT_FUSED 1.0 mm, and a same-input formal Fields report is missing. The saved main-path review proves separate continuous front-layer paths of 1.5 mm and 2.0 mm respectively (IPC-2221 estimates 8.58 C and 5.34 C at 3 A), but excludes branch loads/pad necks and does not override the gate. See design/step12-main-path-review.json. Next work is a terminal-aware capacity check and supported same-board Fields integration, not blindly widening the voltage-sense branch.
docs/explicit-terminal-analysis.md+10@@ -9,3 +9,13 @@ The actual saved board-19 diagnostic at 0.2 mm uses explicit 3 A main paths for This is not a current-gate pass. Main-path boundary conditions omit sense currents and alternate fixture returns. The existing terminal injection uses a 1 mm neighborhood, not exact package contacts. Full branch/auxiliary scenarios, resolution sensitivity and integration with AIFlow's conservative conductor screen remain required. All three hot-part checks still fail in the board-only model. Its Q1 heat is incorrectly constrained to the board for the intended external case-mounted heatsink assembly, which is absent from this solve. These temperatures must not be presented as a prediction of the proposed cooled assembly, and the current results must not be presented as thermal qualification. No finish or fabrication acceptance was recorded.++## Branch and auxiliary checks++The sense-branch diagnostic retains 3 A into F1 and adds 0.2204 mA for a 24 V divider with both resistors at -1 percent. INA226 VBUS uses its documented typical 830 kohm input (28.916 uA at 24 V), explicitly not a guaranteed maximum. ADC leakage is not modeled.++The auxiliary sweep assigns the entire 0.3 A from J3.1 to each consumer in turn: J9.1, U9.1, U9.3, U5.4, U5.5 and L1.1. Peaks range from 21.6 to 24.2 A/mm². This bounds fixed-conductivity linear DC mixtures under the assumed total current; it does not validate that budget or capacitor/boost transient currents. See `design/aux-current-envelope/summary.json`.++An independent centerline resistor calculation and a new isolated AIFlow Rust implementation agree: DUT_POS maximum track rise is 3.542 C or 2.982 C for the two J1 source-layer extremes; DUT_FUSED is 3.933 C. The thin sense branch carries 0.2204 mA, and the 1 mm parallel fuse branch about 0.378 A. The Rust screen also reports maximum barrel density of 33.43 A/mm² for DUT_POS and 11.33 A/mm² for DUT_FUSED, under explicit nominal plating assumptions. Pads are approximated as equipotential central contact regions; filled-copper and actual contact qualification remain separate. These results are not installed gate acceptance.++Fields owner handoff: [PR 6](https://wiki.adom.inc/adom/adom-fields/prs/6), explicitly stacked on PR 5. Source tests, submitted diff and saved-board diagnostics were verified; no shared runtime was changed.
tools/screen_branch_currents.pyadded+89@@ -0,0 +1,89 @@+#!/usr/bin/env python3+"""Project-only resistive centerline diagnostic; not a replacement for filled-copper Fields."""+import hashlib,json,math+from pathlib import Path+import numpy as np+from sexp import parse,find,first+ROOT=Path(__file__).resolve().parents[1]+BOARD=ROOT/'aiflow/run/board-19.kicad_pcb'+SIGMA=58000.0 # S/mm at nominal reference temperature++def solve(edges,injections):+ nodes=sorted({n for a,b,r,meta in edges for n in [a,b]}); ids={n:i for i,n in enumerate(nodes)}+ matrix=np.zeros((len(nodes),len(nodes))); rhs=np.zeros(len(nodes))+ for a,b,r,meta in edges:+ if a==b:continue+ assert r>0+ i,j=ids[a],ids[b];g=1/r+ matrix[i,i]+=g;matrix[j,j]+=g;matrix[i,j]-=g;matrix[j,i]-=g+ for n,a in injections.items():rhs[ids[n]]+=a+ assert abs(sum(injections.values()))<1e-10+ v=np.zeros(len(nodes));v[1:]=np.linalg.solve(matrix[1:,1:],rhs[1:])+ residual=matrix@v-rhs+ assert np.max(np.abs(residual))<1e-8+ return [(v[ids[a]]-v[ids[b]])/r if a!=b else 0 for a,b,r,meta in edges],float(np.max(np.abs(residual)))++# Analytic series and parallel checks prevent current-sharing/unit regressions.+assert np.allclose(np.abs(solve([('a','b',1,{}),('b','c',2,{})],{'a':3,'c':-3})[0]),[3,3])+assert np.allclose(np.abs(solve([('a','b',1,{}),('a','b',2,{})],{'a':3,'b':-3})[0]),[2,1])+b=parse(BOARD.read_text());netnames={str(n[1]):str(n[2]) for n in find(b,'net')}+def net(n):+ v=first(n,'net')[1];return netnames.get(str(v),str(v))+def xy(n,k):return tuple(float(x) for x in first(n,k)[1:3])+def node(layer,p):return (layer,round(p[0],6),round(p[1],6))+allresults=[]+for name in ['DUT_POS','DUT_FUSED']:+ edges=[]; unions={}+ def root(n):+ while n in unions:n=unions[n]+ return n+ def union(a,c):+ a,c=root(a),root(c)+ if a!=c:unions[max(a,c)]=min(a,c)+ for s in find(b,'segment'):+ if net(s)!=name:continue+ a,c=xy(s,'start'),xy(s,'end');width=float(first(s,'width')[1]);layer=str(first(s,'layer')[1]);length=math.dist(a,c)+ edges.append((node(layer,a),node(layer,c),length/(SIGMA*width*.035),{'kind':'track','id':str(first(s,'uuid')[1]),'widthMm':width,'lengthMm':length,'layer':layer}))+ for v in find(b,'via'):+ if net(v)!=name:continue+ at=xy(v,'at');d=float(first(v,'drill')[1]);plating=.025+ area=math.pi*((d/2+plating)**2-(d/2)**2)+ edges.append((node('F.Cu',at),node('B.Cu',at),1.6/(SIGMA*area),{'kind':'via','id':str(first(v,'uuid')[1]),'barrelAreaMm2':area}))+ # This board's flagged nets have axis-aligned pads. Reject other orientations.+ pads={}+ for f in find(b,'footprint'):+ ref=next((str(p[2]) for p in find(f,'property') if p[1]=='Reference'),'')+ at=first(f,'at');fx,fy=map(float,at[1:3]);angle=float(at[3]) if len(at)>3 else 0+ for p in find(f,'pad'):+ if not first(p,'net') or net(p)!=name:continue+ assert angle % 180 == 0,(ref,'only 0/180 degree footprints supported in this diagnostic')+ px,py=xy(p,'at');sign=1 if angle % 360 == 0 else -1;cx,cy=fx+sign*px,fy+sign*py;size=xy(p,'size');padnum=str(p[1]);pads[(ref,padnum)]=(cx,cy)+ layers=['F.Cu','B.Cu'] if p[2]=='thru_hole' else [str(first(p,'layers')[1])]+ for layer in layers:+ center=node(layer,(cx,cy))+ # Only endpoints in a conservative central disk are equipotential here.+ for edge in edges:+ for n in edge[:2]:+ if n[0]==layer and math.dist(n[1:],(cx,cy))<=min(size)/2:union(center,n)+ if p[2]=='thru_hole':+ drill=float(first(p,'drill')[1]);area=math.pi*((drill/2+.025)**2-(drill/2)**2)+ edges.append((node('F.Cu',(cx,cy)),node('B.Cu',(cx,cy)),1.6/(SIGMA*area),{'kind':'plated-pad','pin':ref+'.'+padnum,'barrelAreaMm2':area}))+ edges=[(root(a),root(c),r,m) for a,c,r,m in edges]+ for source_layer in (['F.Cu','B.Cu'] if name=='DUT_POS' else ['F.Cu']):+ if name=='DUT_POS':+ sense=24/(110000*.99)+ points=[(source_layer,pads[('J1','1')],3+sense),('F.Cu',pads[('F1','1')],-3),('F.Cu',pads[('R24','1')],-sense)]+ else:points=[('F.Cu',pads[('F1','2')],3),('F.Cu',pads[('D1','2')],-3)]+ injection={}+ for layer,p,amps in points:injection[root(node(layer,p))]=injection.get(root(node(layer,p)),0)+amps+ currents,residual=solve(edges,injection);rows=[]+ for e,current in zip(edges,currents):+ m=dict(e[3]);m['amps']=abs(float(current));m['resistanceOhm']=e[2]+ if m['kind']=='track':+ area=m['widthMm']*.035*1550.0031+ m['ipc2221RiseC']=(m['amps']/(.048*area**.725))**(1/.44)+ rows.append(m)+ allresults.append({'net':name,'sourceLayer':source_layer,'kclMaxResidualA':residual,'conductors':rows,'peakTrackRiseC':max(r.get('ipc2221RiseC',0) for r in rows)})+report={'formalAcceptance':False,'kind':'resistive-centerline-branch-diagnostic','boardSha256':hashlib.sha256(BOARD.read_bytes()).hexdigest(),'cases':allresults,'limits':['Tracks modeled as uniform straight resistors; no filled polygon current distribution','Pad central regions treated equipotential; pad necks/contact spreading not qualified','35 um copper, 25 um barrel plating, 1.6 mm barrels assumed, not measured','Both J1 source-layer extremes checked; actual contact distribution unknown','No thermal coupling, conductivity-temperature feedback or pulse heating','This diagnostic does not override AIFlow or Fields gates']}+(ROOT/'design/step12-resistive-branch-summary.json').write_text(json.dumps(report,indent=2)+'\n')+for r in allresults:print(r['net'],r['sourceLayer'],'peak track rise',round(r['peakTrackRiseC'],3),'C')