AI Flow

(version 1)

# adom-aiflow rules profile: jlcpcb-2L
# JLCPCB standard 2-layer (1 oz outer copper, 1.6 mm FR4) as KiCad custom rules, installed with
#   adom-aiflow rules install --profile jlcpcb
# Source: JLCPCB PCB capabilities, https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-29).
# The page's absolute minimums are quoted beside each rule; this profile uses JLCPCB's long-standing
# standard values above them (5/5 mil tracks, 0.3 mm drills, 0.6 mm vias), so a board passing it
# needs no small-feature upgrade. Tighten a rule only when the order pays for the upgrade.

# Tracks and spacing. Page: "Min. track width and spacing (1 oz): 0.10 / 0.10 mm (4 / 4 mil)"
# for 1-2 layers; 2 oz is 0.16 / 0.16 mm.
(rule "jlcpcb track width"
  (layer outer)
  (condition "A.Type == 'Track'")
  (constraint track_width (min 0.127mm)))

(rule "jlcpcb clearance"
  (constraint clearance (min 0.127mm)))

# Drills. Page: "Min. Via hole size/diameter: 0.15/0.25mm"; 0.1 and 0.15 mm holes "cost more".
(rule "jlcpcb drill"
  (constraint hole_size (min 0.3mm)))

# Non-plated holes. Page: "Min NPTH size: 0.50mm".
(rule "jlcpcb npth"
  (condition "A.Type == 'Pad' && !A.isPlated()")
  (constraint hole_size (min 0.5mm)))

# Vias. Page: via diameter "0.1mm (0.15mm preferred) larger than Via hole size".
(rule "jlcpcb via diameter"
  (condition "A.Type == 'Via'")
  (constraint via_diameter (min 0.6mm))
  (constraint annular_width (min 0.15mm)))

# Plated through-hole pads. Page: "PTH annular ring (1 oz): recommended 0.25 mm or above;
# absolute minimum 0.18 mm".
(rule "jlcpcb pth annular ring"
  (condition "A.Type == 'Pad' && A.isPlated()")
  (constraint annular_width (min 0.18mm)))

# Hole to hole. Page: "Via Hole-to-Hole Spacing: 0.2mm", "Pad Hole-to-Hole Spacing: 0.45mm".
(rule "jlcpcb via hole to hole"
  (constraint hole_to_hole (min 0.2mm)))

(rule "jlcpcb pad hole to hole"
  (condition "A.Type == 'Pad' && B.Type == 'Pad'")
  (constraint hole_to_hole (min 0.45mm)))

# Copper to board edge. Page: copper clearance from routed edges ">= 0.2 mm", from V-cut edges
# ">= 0.4 mm". 0.3 mm keeps margin on routed edges. The page gives no separate hole-to-edge
# figure; plated holes carry copper, so this rule covers them.
(rule "jlcpcb copper to edge"
  (constraint edge_clearance (min 0.3mm)))

# Silkscreen. Page: "Min line width >= 0.15mm", "Min text height 40 mil (1.0mm)"; Adom has tested 0.8 mm text at JLCPCB and it prints legibly (2026-10-08).
(rule "jlcpcb silk text"
  (layer "F.SilkS")
  (constraint text_thickness (min 0.153mm))
  (constraint text_height (min 0.8mm)))

(rule "jlcpcb silk text back"
  (layer "B.SilkS")
  (constraint text_thickness (min 0.153mm))
  (constraint text_height (min 0.8mm)))