AI Flow

{
  "board": "ESC G431 (Adom molecule: STM32G431, DRV8300, six BSC016N06NS, TPSM365 buck, INA181 current sense), 64 x 74 mm, 4 layers",
  "copperUm": 35,
  "clearance": 0.2,
  "edgeClearance": 0.5,
  "inheritedErrors": 13,
  "inheritedErrorsNote": "six malformed MOSFET courtyards and seven U2 pad clearances come from the source libraries; they are counted separately and never fixed by the flow",
  "fixedRefs": [
    "MP1",
    "MP2",
    "MP3",
    "MP4",
    "MC1",
    "MC2",
    "MC3",
    "MC4",
    "MC5",
    "MC6",
    "MC7",
    "MC8",
    "MC9",
    "MC10",
    "MC11",
    "MC12",
    "MC13",
    "MC14",
    "MC15",
    "MC16",
    "MC17",
    "MC18",
    "MC19",
    "MC20",
    "MC21",
    "MC22",
    "MC23"
  ],
  "planes": {
    "GND": "In1.Cu",
    "+3V3": "In2.Cu"
  },
  "wideNets": {
    "+VBAT": [
      1.0,
      0.5,
      0.25
    ],
    "/DRV_SHA": [
      1.0,
      0.5,
      0.25
    ],
    "/DRV_SHB": [
      1.0,
      0.5,
      0.25
    ],
    "/DRV_SHC": [
      1.0,
      0.5,
      0.25
    ],
    "GND_OUT": [
      1.0,
      0.5,
      0.25
    ]
  },
  "midNets": {
    "+5V": [
      0.5,
      0.25
    ],
    "+12V": [
      0.5,
      0.25
    ]
  },
  "kelvin": {
    "U6.3": "R32.2",
    "U6.4": "R32.1"
  },
  "kelvinNote": "INA181 IN- (pad 3) taps the shunt's GND pad, IN+ (pad 4) taps its GND_OUT pad; dedicated traces, no plane stub, pour keepouts along them",
  "planeUnder": [
    {
      "layer": "B.Cu",
      "net": "GND",
      "around": [
        "U6",
        "R32"
      ],
      "margin": 1.0,
      "name": "GND under the current sense"
    }
  ],
  "planeUnderNote": "layer policy: B.Cu under the sense amplifier and its shunt belongs to GND. The router treats each region as a keepout for every other net on that layer (and for other nets' vias); the gate reports any other-net track, via or zone inside it. \"around\" takes parts or pads (the pad box grown by margin, default 1.0 mm); \"polygon\": [[x, y], ...] gives the region exactly. On a 2-layer power board list the hot loop: the IC and its input caps.",
  "chains": [
    {
      "refs": [
        "R1",
        "R2"
      ],
      "direction": "down"
    }
  ],
  "chainsNote": "series chains for place pack, in electrical order (a divider: VOUT-R1-FBM-R2-FB). pack lays the members on one line from the first member's wish, on one axis, each turned so the pads on the shared net face each other, and reports which chains were honoured. A plain [\"R1\", \"R2\"] takes the direction from the first to the last wish. Shape only here: list this board's own divider parts.",
  "loads": {
    "+VBAT": {
      "amps": 20,
      "maxRiseC": 10
    },
    "/DRV_SHA": {
      "amps": 20,
      "maxRiseC": 10
    },
    "/DRV_SHB": {
      "amps": 20,
      "maxRiseC": 10
    },
    "/DRV_SHC": {
      "amps": 20,
      "maxRiseC": 10
    },
    "GND_OUT": {
      "amps": 20,
      "maxRiseC": 10
    },
    "+12V": {
      "amps": 0.5
    },
    "+5V": {
      "amps": 0.5
    }
  },
  "hot": {
    "Q1": {
      "watts": 0.6,
      "tabNet": "+VBAT"
    },
    "Q3": {
      "watts": 0.6,
      "tabNet": "+VBAT"
    },
    "Q5": {
      "watts": 0.6,
      "tabNet": "+VBAT"
    },
    "Q2": {
      "watts": 0.6,
      "tabNet": "/DRV_SHA"
    },
    "Q4": {
      "watts": 0.6,
      "tabNet": "/DRV_SHB"
    },
    "Q6": {
      "watts": 0.6,
      "tabNet": "/DRV_SHC"
    },
    "U1": {
      "watts": 0.5,
      "tabNet": "+VBAT",
      "note": "SOT-89 pad 2 (the tab) is +VBAT, the input; the +VBAT F.Cu block has a tongue down to it"
    }
  },
  "pours": [
    {
      "net": "GND",
      "outline": true,
      "layers": [
        "F.Cu",
        "B.Cu"
      ],
      "priority": 0,
      "connection": "thermal",
      "thermalGap": 0.3,
      "thermalBridge": 0.35,
      "name": "GND outer pour (ablation: keep the copper)"
    },
    {
      "net": "+VBAT",
      "polygon": [
        [
          127.58,
          59.8
        ],
        [
          159.13,
          59.8
        ],
        [
          159.13,
          90.9
        ],
        [
          140.0,
          90.9
        ],
        [
          140.0,
          93.4
        ],
        [
          131.0,
          93.4
        ],
        [
          131.0,
          90.9
        ],
        [
          127.58,
          90.9
        ]
      ],
      "layers": [
        "F.Cu"
      ],
      "priority": 2,
      "connection": "solid",
      "name": "+VBAT rail block F.Cu (tongue to U1's tab)"
    },
    {
      "net": "+VBAT",
      "polygon": [
        [
          127.58,
          59.8
        ],
        [
          159.13,
          59.8
        ],
        [
          159.13,
          93.0
        ],
        [
          160.6,
          93.0
        ],
        [
          160.6,
          111.0
        ],
        [
          153.3,
          111.0
        ],
        [
          153.3,
          95.0
        ],
        [
          127.58,
          95.0
        ]
      ],
      "layers": [
        "B.Cu"
      ],
      "priority": 2,
      "connection": "solid",
      "name": "+VBAT rail block, high-side tab column and bypass B.Cu"
    },
    {
      "net": "/DRV_SHA",
      "around": [
        "Q1.1",
        "Q2.5",
        "MC5"
      ],
      "margin": 0.6,
      "layers": [
        "F.Cu"
      ],
      "priority": 3,
      "connection": "solid",
      "name": "/DRV_SHA phase F.Cu"
    },
    {
      "net": "/DRV_SHB",
      "layers": [
        "F.Cu"
      ],
      "priority": 3,
      "connection": "solid",
      "name": "/DRV_SHB phase F.Cu (with the free band right of Q3)",
      "polygon": [
        [
          150.67,
          92.57
        ],
        [
          159.5,
          92.57
        ],
        [
          159.5,
          87.0
        ],
        [
          166.8,
          87.0
        ],
        [
          166.8,
          104.91
        ],
        [
          150.67,
          104.91
        ]
      ]
    },
    {
      "net": "/DRV_SHC",
      "around": [
        "Q5.1",
        "Q6.5",
        "MC11"
      ],
      "margin": 0.6,
      "layers": [
        "F.Cu"
      ],
      "priority": 3,
      "connection": "solid",
      "name": "/DRV_SHC phase F.Cu"
    },
    {
      "net": "GND_OUT",
      "around": [
        "MC3",
        "R32.1"
      ],
      "margin": 0.5,
      "layers": [
        "F.Cu",
        "B.Cu"
      ],
      "priority": 3,
      "connection": "solid",
      "name": "GND_OUT return"
    },
    {
      "net": "/DRV_SHA",
      "polygon": [
        [
          126.0,
          111.3
        ],
        [
          166.8,
          111.3
        ],
        [
          166.8,
          131.0
        ],
        [
          126.0,
          131.0
        ]
      ],
      "layers": [
        "B.Cu"
      ],
      "priority": 3,
      "connection": "solid",
      "name": "/DRV_SHA heat spreader B.Cu (under Q2 and the board's bottom band)"
    },
    {
      "net": "/DRV_SHB",
      "polygon": [
        [
          126.0,
          95.2
        ],
        [
          152.9,
          95.2
        ],
        [
          152.9,
          99.3
        ],
        [
          159.0,
          99.3
        ],
        [
          159.0,
          104.7
        ],
        [
          152.9,
          104.7
        ],
        [
          152.9,
          106.0
        ],
        [
          126.0,
          106.0
        ]
      ],
      "layers": [
        "B.Cu"
      ],
      "priority": 3,
      "connection": "solid",
      "name": "/DRV_SHB heat spreader B.Cu (left arm and the Q4 tab bridge)"
    },
    {
      "net": "/DRV_SHB",
      "polygon": [
        [
          161.0,
          87.0
        ],
        [
          166.8,
          87.0
        ],
        [
          166.8,
          108.6
        ],
        [
          161.0,
          108.6
        ]
      ],
      "layers": [
        "B.Cu"
      ],
      "priority": 3,
      "connection": "solid",
      "name": "/DRV_SHB heat spreader B.Cu (right arm, MC9 to above Q1)"
    },
    {
      "net": "/DRV_SHC",
      "polygon": [
        [
          131.0,
          79.0
        ],
        [
          159.0,
          79.0
        ],
        [
          159.0,
          86.5
        ],
        [
          152.9,
          86.5
        ],
        [
          152.9,
          93.0
        ],
        [
          131.0,
          93.0
        ]
      ],
      "layers": [
        "B.Cu"
      ],
      "priority": 3,
      "connection": "solid",
      "name": "/DRV_SHC heat spreader B.Cu (left arm and the Q6 tab)"
    },
    {
      "net": "/DRV_SHC",
      "polygon": [
        [
          159.6,
          73.57
        ],
        [
          166.8,
          73.57
        ],
        [
          166.8,
          86.41
        ],
        [
          159.6,
          86.41
        ]
      ],
      "layers": [
        "B.Cu"
      ],
      "priority": 3,
      "connection": "solid",
      "name": "/DRV_SHC heat spreader B.Cu (right arm at MC11)"
    }
  ],
  "solidAt": [
    "C45.2",
    "C43.2",
    "JP1.1"
  ],
  "thermalVias": [
    {
      "pad": "Q1.5",
      "net": "+VBAT",
      "count": 2
    },
    {
      "pad": "Q3.5",
      "net": "+VBAT",
      "count": 2
    },
    {
      "pad": "Q5.5",
      "net": "+VBAT",
      "count": 2
    },
    {
      "pad": "Q2.5",
      "net": "/DRV_SHA",
      "count": 2
    },
    {
      "pad": "Q4.5",
      "net": "/DRV_SHB",
      "count": 2
    },
    {
      "pad": "Q6.5",
      "net": "/DRV_SHC",
      "count": 2
    }
  ],
  "stitchVias": [
    {
      "net": "+VBAT",
      "x": 157.5,
      "y": 67.5
    },
    {
      "net": "+VBAT",
      "x": 145.5,
      "y": 61.0
    }
  ],
  "notPoured": [
    "/DRV_BSTA",
    "/DRV_BSTB",
    "/DRV_BSTC",
    "/SW",
    "/HSE_IN",
    "/HSE_OUT",
    "/COMP1_INM_IO1_BEMF_B",
    "/COMP1_INM_IO2_BEMF_C",
    "/COMP2_INM_IO1_BEMF_A",
    "/VBAT_SENSE",
    "/IBAT_SENSE",
    "+3V3",
    "/VDDA"
  ],
  "notPouredNote": "switching and bootstrap nodes, the crystal, the BEMF dividers and comparator inputs, the sense taps; +3V3 and /VDDA have the In2.Cu plane",
  "stitchViasNote": "inside both +VBAT rail blocks (F.Cu and B.Cu) and clear of other copper; a stitching via outside the pour is an unconnected item",
  "poursNote": "Phase current flows on F.Cu (source pads, low-side tab and connector are all F.Cu); the B.Cu phase zones are heat spreaders under the low-side tabs, fed by thermal vias. The +VBAT B.Cu block keeps a column under the high-side tabs and a bypass strip right of the FET column so Q1's tab copper stays connected past the Q4 tab bridge.",
  "hotNote": "BSC016N06NS at 20 A phase current: I2R at 3 mOhm hot (Rds(on) 1.6 mOhm typ at 25 C) over one third of the electrical cycle (six-step) is 0.4 W, plus about 0.2 W of switching at 24 kHz: 0.6 W per FET. U1 is a linear regulator on the +VBAT tab: 0.5 W.",
  "hotMaxRiseC": 60,
  "hotMaxRiseNote": "the tab may sit 60 C above ambient at the stated dissipation (theta from the 40 C/W per square inch outer-copper heuristic of 0.1)",
  "fabNote": "3rd party fab (copper ablation: keep as much copper as the electrical rules allow)",
  "fab": {
    "rules": "fab",
    "target": "fab"
  },
  "fabRulesNote": "fab.rules picks the DRC rules profile: \"fab\" = the project's own .kicad_dru for the 3rd party fab (private, never shipped), \"jlcpcb\" = `rules install --profile jlcpcb` copies the shipped JLCPCB 2-layer rules; gate and finish refuse a mismatch. fab.target (or sourcing.profile) picks the sourcing profile for `sourcing check`.",
  "sourcing": {
    "profile": "fab"
  },
  "molecule": {
    "pin": "medium",
    "gridMm": 2,
    "edgeMarginMm": 2,
    "cornerPinsNet": "GND"
  },
  "moleculeNote": "present when the board is an Adom molecule: `molecule check` (and place check, gate, finish) require MP1 to MP4 machine pins with MP1 front-left, the pin rectangle and every contact on gridMm from MP1 (4 mm multiples warned for LrgMed scaffolds), edgeMarginMm to the outline, and fixedRefs where the start board had them; pinPadMm/pinDrillMm override the pin size.",
  "requireEvidence": [
    "calcs",
    "simulation"
  ],
  "requireEvidenceNote": "kinds `evidence add` must have recorded before finish: calcs (the design equations), simulation (a failing result is refused), vendor-model (a PSpice/LTspice run from adom/adom-spice-skillpack)."
}