ADN8831ACPZ-REEL7

@@ -53,7 +53,7 @@         "number": "1",         "name": "ILIMC",         "type": "input",-        "description": "Sets TEC cooling current limit with input voltage range VREF/2 to VDD \u2212 1 V."+        "description": "Sets TEC cooling current limit with input voltage range VREF/2 to VDD − 1 V."       },       {         "number": "2",@@ -107,13 +107,13 @@         "number": "10",         "name": "PHASE",         "type": "input",-        "description": "Clock phase adjustment input with adjustment range 50\u00b0 to 330\u00b0 for SYNCO output phase relative to SYNCI/SD clock."+        "description": "Clock phase adjustment input with adjustment range 50° to 330° for SYNCO output phase relative to SYNCI/SD clock."       },       {         "number": "11",         "name": "TMPGD",         "type": "output",-        "description": "Temperature good indicator logic output active high when OUT1 voltage is within \u00b1100 mV of IN2P setpoint voltage."+        "description": "Temperature good indicator logic output active high when OUT1 voltage is within ±100 mV of IN2P setpoint voltage."       },       {         "number": "12",@@ -161,7 +161,7 @@         "number": "19",         "name": "SPGATE",         "type": "output",-        "description": "PWM driver output to external PMOS gate with output resistance 100 \u03a9 typical."+        "description": "PWM driver output to external PMOS gate with output resistance 100 Ω typical."       },       {         "number": "20",@@ -173,7 +173,7 @@         "number": "21",         "name": "SNGATE",         "type": "output",-        "description": "PWM driver output to external NMOS gate with output resistance 6 \u03a9 typical at VDD = 3.0 V."+        "description": "PWM driver output to external NMOS gate with output resistance 6 Ω typical at VDD = 3.0 V."       },       {         "number": "22",@@ -197,13 +197,13 @@         "number": "25",         "name": "LPGATE",         "type": "output",-        "description": "Linear driver output to external PMOS gate with output resistance 100 \u03a9 at 2 mA."+        "description": "Linear driver output to external PMOS gate with output resistance 100 Ω at 2 mA."       },       {         "number": "26",         "name": "LNGATE",         "type": "output",-        "description": "Linear driver output to external NMOS gate with output resistance 200 \u03a9 at 2 mA."+        "description": "Linear driver output to external NMOS gate with output resistance 200 Ω at 2 mA."       },       {         "number": "27",@@ -282,6 +282,46 @@     "viewers": {       "symbol": "viewers/symbol.html",       "footprint": "viewers/footprint.html"-    }+    },+    "models_3d": [+      {+        "file": "adn8831acpz-reel7.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          5.0,+          5.0,+          0.875+        ],+        "zmin_mm": 0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "adn8831acpz-reel7-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          5.0,+          5.0,+          0.875+        ],+        "zmin_mm": 0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "21a53f7aa7b8a2a7560ce057c79f6f823b8cde7e9989758629d4032b2cafb1b7",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]   }-}\ No newline at end of file+}