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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADN8831ACPZ-REEL7

Analog Devices · Power Management - Specialized · LFCSP-32(5x5)

ADN8831ACPZ-REEL7 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ILIMC	input	Sets TEC cooling current limit with input voltage range VREF/2 to VDD − 1 V.
2	IN1P	input	Noninverting input to error amplifier with common-mode voltage range 0 to VDD.
3	IN1N	input	Inverting input to error amplifier with common-mode voltage range 0 to VDD.
4	OUT1	output	Output of error amplifier with voltage swing 0 to VDD V.
5	IN2P	input	Noninverting input to compensation amplifier with common-mode voltage range 0 to VDD.
6	IN2N	input	Inverting input to compensation amplifier with common-mode voltage range 0 to VDD.
7	OUT2	output	Output of compensation amplifier with voltage swing 0 to VDD V.
8	VREF	power_in	2.5 V voltage reference output with typical value 2.37 to 2.57 V at zero load current.
9	AVDD	power_in	Analog power supply input with voltage range 3.0 V to 5.5 V for nondriver sections.
10	PHASE	input	Clock phase adjustment input with adjustment range 50° to 330° for SYNCO output phase relative to SYNCI/SD clock.
11	TMPGD	output	Temperature good indicator logic output active high when OUT1 voltage is within ±100 mV of IN2P setpoint voltage.
12	AGND	power_in	Analog ground connection point for low-noise grounding and interface to exposed pad.
13	FREQ	input	Switching frequency programming input using external resistor to set frequency in range 200 to 1000 kHz.
14	SS/SB	input	Soft start time and standby mode control input; pull low for standby mode, capacitor sets soft start timing.
15	SYNCO	output	Clock output with phase adjusted by PHASE input for driving SYNCI/SD of other ADN8831 devices.
16	SYNCI/SD	input	Optional external clock input or shutdown control; pull low for shutdown mode, pull high to enable operation.
17	COMPOSC	output	Oscillator compensation output; connect to PVDD for free-run mode or R-C network for external clock synchronization.
18	PVDD	power_in	Power supply input with voltage range 3.0 V to 5.5 V for output driver sections.
19	SPGATE	output	PWM driver output to external PMOS gate with output resistance 100 Ω typical.
20	SW	input	Analog input connection to PWM FET drains for voltage monitoring.
21	SNGATE	output	PWM driver output to external NMOS gate with output resistance 6 Ω typical at VDD = 3.0 V.
22	PGND	power_in	Power ground connection for external NMOS devices; interface to digital ground plane.
23	SFB	input	PWM feedback input connected to TEC module negative terminal with input range 0 to VDD.
24	COMPSW	input	Compensation pin for switching amplifier feedback network.
25	LPGATE	output	Linear driver output to external PMOS gate with output resistance 100 Ω at 2 mA.
26	LNGATE	output	Linear driver output to external NMOS gate with output resistance 200 Ω at 2 mA.
27	LFB	input	Linear feedback input from H-bridge transistor output and current sense resistor with range 0 to VDD.
28	CS	input	Linear feedback current sense input connected to TEC module positive terminal.
29	ITEC	output	TEC current monitor output with voltage proportional to actual current through TEC module.
30	VTEC	output	TEC voltage monitor output with voltage proportional to actual voltage across TEC module.
31	VLIM	input	Maximum TEC voltage limit programming input with voltage range 0 to VDD.
32	ILIMH	input	TEC heating current limit programming input with voltage range 0.1 V to VREF/2.
33	EP	power_in	Exposed metal pad at back of package connected to AGND (Pin 12) and associated PCB ground plane for thermal and ground management.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-32(5x5)
Category	Power Management (PMIC)
Pins	33

CAD (KiCad official)

Symbol: ADN8831ACPZ-REEL7
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
3D model files: adn8831acpz-reel7-etched.step / adn8831acpz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adn8831acpz-reel7.step / adn8831acpz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (18 pp, sha256 fe3a860f8d3291fc, retrieved 2026-09-22, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF