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ADN8831ACPZ-REEL7
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Analog Devices Power Management - Specialized, LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+69@@ -0,0 +1,69 @@+# ADN8831ACPZ-REEL7++**Analog Devices** · Power Management - Specialized · LFCSP-32(5x5)++ADN8831ACPZ-REEL7 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | ILIMC | input | Sets TEC cooling current limit with input voltage range VREF/2 to VDD − 1 V. |+| 2 | IN1P | input | Noninverting input to error amplifier with common-mode voltage range 0 to VDD. |+| 3 | IN1N | input | Inverting input to error amplifier with common-mode voltage range 0 to VDD. |+| 4 | OUT1 | output | Output of error amplifier with voltage swing 0 to VDD V. |+| 5 | IN2P | input | Noninverting input to compensation amplifier with common-mode voltage range 0 to VDD. |+| 6 | IN2N | input | Inverting input to compensation amplifier with common-mode voltage range 0 to VDD. |+| 7 | OUT2 | output | Output of compensation amplifier with voltage swing 0 to VDD V. |+| 8 | VREF | power_in | 2.5 V voltage reference output with typical value 2.37 to 2.57 V at zero load current. |+| 9 | AVDD | power_in | Analog power supply input with voltage range 3.0 V to 5.5 V for nondriver sections. |+| 10 | PHASE | input | Clock phase adjustment input with adjustment range 50° to 330° for SYNCO output phase relative to SYNCI/SD clock. |+| 11 | TMPGD | output | Temperature good indicator logic output active high when OUT1 voltage is within ±100 mV of IN2P setpoint voltage. |+| 12 | AGND | power_in | Analog ground connection point for low-noise grounding and interface to exposed pad. |+| 13 | FREQ | input | Switching frequency programming input using external resistor to set frequency in range 200 to 1000 kHz. |+| 14 | SS/SB | input | Soft start time and standby mode control input; pull low for standby mode, capacitor sets soft start timing. |+| 15 | SYNCO | output | Clock output with phase adjusted by PHASE input for driving SYNCI/SD of other ADN8831 devices. |+| 16 | SYNCI/SD | input | Optional external clock input or shutdown control; pull low for shutdown mode, pull high to enable operation. |+| 17 | COMPOSC | output | Oscillator compensation output; connect to PVDD for free-run mode or R-C network for external clock synchronization. |+| 18 | PVDD | power_in | Power supply input with voltage range 3.0 V to 5.5 V for output driver sections. |+| 19 | SPGATE | output | PWM driver output to external PMOS gate with output resistance 100 Ω typical. |+| 20 | SW | input | Analog input connection to PWM FET drains for voltage monitoring. |+| 21 | SNGATE | output | PWM driver output to external NMOS gate with output resistance 6 Ω typical at VDD = 3.0 V. |+| 22 | PGND | power_in | Power ground connection for external NMOS devices; interface to digital ground plane. |+| 23 | SFB | input | PWM feedback input connected to TEC module negative terminal with input range 0 to VDD. |+| 24 | COMPSW | input | Compensation pin for switching amplifier feedback network. |+| 25 | LPGATE | output | Linear driver output to external PMOS gate with output resistance 100 Ω at 2 mA. |+| 26 | LNGATE | output | Linear driver output to external NMOS gate with output resistance 200 Ω at 2 mA. |+| 27 | LFB | input | Linear feedback input from H-bridge transistor output and current sense resistor with range 0 to VDD. |+| 28 | CS | input | Linear feedback current sense input connected to TEC module positive terminal. |+| 29 | ITEC | output | TEC current monitor output with voltage proportional to actual current through TEC module. |+| 30 | VTEC | output | TEC voltage monitor output with voltage proportional to actual voltage across TEC module. |+| 31 | VLIM | input | Maximum TEC voltage limit programming input with voltage range 0 to VDD. |+| 32 | ILIMH | input | TEC heating current limit programming input with voltage range 0.1 V to VREF/2. |+| 33 | EP | power_in | Exposed metal pad at back of package connected to AGND (Pin 12) and associated PCB ground plane for thermal and ground management. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LFCSP-32(5x5) |+| Category | Power Management (PMIC) |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `ADN8831ACPZ-REEL7`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)+- 3D model files: `adn8831acpz-reel7-etched.step` / `adn8831acpz-reel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adn8831acpz-reel7.step` / `adn8831acpz-reel7.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883532206231552) (18 pp, sha256 `fe3a860f8d3291fc`, retrieved 2026-09-22, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adn8831acpz-reel7-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "adn8831acpz-reel7",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "adn8831acpz-reel7.kicad_sym",+ "adn8831acpz-reel7.kicad_mod",+ "adn8831acpz-reel7.glb",+ "adn8831acpz-reel7.step",+ "adn8831acpz-reel7.lbr",+ "docs/hero.png",+ "docs/adn8831acpz-reel7-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADN8831ACPZ-REEL7",+ "manufacturer": "Analog Devices",+ "package": "LFCSP-32(5x5)",+ "pin_count": 33,+ "category": "Power Management (PMIC)",+ "subcategory": "Power Management - Specialized",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883532206231552",+ "parts": {+ "symbol": "adn8831acpz-reel7.kicad_sym",+ "footprint": "adn8831acpz-reel7.kicad_mod",+ "model_3d": "adn8831acpz-reel7-etched.glb",+ "model_3d_plain": "adn8831acpz-reel7.glb",+ "model_3d_step": "adn8831acpz-reel7-etched.step",+ "model_3d_step_plain": "adn8831acpz-reel7.step",+ "lbr": "adn8831acpz-reel7.lbr"+ },+ "distributor_links": {+ "lcsc": "C73175"+ },+ "pins": [+ {+ "number": "1",+ "name": "ILIMC",+ "type": "input",+ "description": "Sets TEC cooling current limit with input voltage range VREF/2 to VDD − 1 V."+ },+ {+ "number": "2",+ "name": "IN1P",+ "type": "input",+ "description": "Noninverting input to error amplifier with common-mode voltage range 0 to VDD."+ },+ {+ "number": "3",+ "name": "IN1N",+ "type": "input",+ "description": "Inverting input to error amplifier with common-mode voltage range 0 to VDD."+ },+ {+ "number": "4",+ "name": "OUT1",+ "type": "output",+ "description": "Output of error amplifier with voltage swing 0 to VDD V."+ },+ {+ "number": "5",+ "name": "IN2P",+ "type": "input",+ "description": "Noninverting input to compensation amplifier with common-mode voltage range 0 to VDD."+ },+ {+ "number": "6",+ "name": "IN2N",+ "type": "input",+ "description": "Inverting input to compensation amplifier with common-mode voltage range 0 to VDD."+ },+ {+ "number": "7",+ "name": "OUT2",+ "type": "output",+ "description": "Output of compensation amplifier with voltage swing 0 to VDD V."+ },+ {+ "number": "8",+ "name": "VREF",+ "type": "power_in",+ "description": "2.5 V voltage reference output with typical value 2.37 to 2.57 V at zero load current."+ },+ {+ "number": "9",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply input with voltage range 3.0 V to 5.5 V for nondriver sections."+ },+ {+ "number": "10",+ "name": "PHASE",+ "type": "input",+ "description": "Clock phase adjustment input with adjustment range 50° to 330° for SYNCO output phase relative to SYNCI/SD clock."+ },+ {+ "number": "11",+ "name": "TMPGD",+ "type": "output",+ "description": "Temperature good indicator logic output active high when OUT1 voltage is within ±100 mV of IN2P setpoint voltage."+ },+ {+ "number": "12",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground connection point for low-noise grounding and interface to exposed pad."+ },+ {+ "number": "13",+ "name": "FREQ",+ "type": "input",+ "description": "Switching frequency programming input using external resistor to set frequency in range 200 to 1000 kHz."+ },+ {+ "number": "14",+ "name": "SS/SB",+ "type": "input",+ "description": "Soft start time and standby mode control input; pull low for standby mode, capacitor sets soft start timing."+ },+ {+ "number": "15",+ "name": "SYNCO",+ "type": "output",+ "description": "Clock output with phase adjusted by PHASE input for driving SYNCI/SD of other ADN8831 devices."+ },+ {+ "number": "16",+ "name": "SYNCI/SD",+ "type": "input",+ "description": "Optional external clock input or shutdown control; pull low for shutdown mode, pull high to enable operation."+ },+ {+ "number": "17",+ "name": "COMPOSC",+ "type": "output",+ "description": "Oscillator compensation output; connect to PVDD for free-run mode or R-C network for external clock synchronization."+ },+ {+ "number": "18",+ "name": "PVDD",+ "type": "power_in",+ "description": "Power supply input with voltage range 3.0 V to 5.5 V for output driver sections."+ },+ {+ "number": "19",+ "name": "SPGATE",+ "type": "output",+ "description": "PWM driver output to external PMOS gate with output resistance 100 Ω typical."+ },+ {+ "number": "20",+ "name": "SW",+ "type": "input",+ "description": "Analog input connection to PWM FET drains for voltage monitoring."+ },+ {+ "number": "21",+ "name": "SNGATE",+ "type": "output",+ "description": "PWM driver output to external NMOS gate with output resistance 6 Ω typical at VDD = 3.0 V."+ },+ {+ "number": "22",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground connection for external NMOS devices; interface to digital ground plane."+ },+ {+ "number": "23",+ "name": "SFB",+ "type": "input",+ "description": "PWM feedback input connected to TEC module negative terminal with input range 0 to VDD."+ },+ {+ "number": "24",+ "name": "COMPSW",+ "type": "input",+ "description": "Compensation pin for switching amplifier feedback network."+ },+ {+ "number": "25",+ "name": "LPGATE",+ "type": "output",+ "description": "Linear driver output to external PMOS gate with output resistance 100 Ω at 2 mA."+ },+ {+ "number": "26",+ "name": "LNGATE",+ "type": "output",+ "description": "Linear driver output to external NMOS gate with output resistance 200 Ω at 2 mA."+ },+ {+ "number": "27",+ "name": "LFB",+ "type": "input",+ "description": "Linear feedback input from H-bridge transistor output and current sense resistor with range 0 to VDD."+ },+ {+ "number": "28",+ "name": "CS",+ "type": "input",+ "description": "Linear feedback current sense input connected to TEC module positive terminal."+ },+ {+ "number": "29",+ "name": "ITEC",+ "type": "output",+ "description": "TEC current monitor output with voltage proportional to actual current through TEC module."+ },+ {+ "number": "30",+ "name": "VTEC",+ "type": "output",+ "description": "TEC voltage monitor output with voltage proportional to actual voltage across TEC module."+ },+ {+ "number": "31",+ "name": "VLIM",+ "type": "input",+ "description": "Maximum TEC voltage limit programming input with voltage range 0 to VDD."+ },+ {+ "number": "32",+ "name": "ILIMH",+ "type": "input",+ "description": "TEC heating current limit programming input with voltage range 0.1 V to VREF/2."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "power_in",+ "description": "Exposed metal pad at back of package connected to AGND (Pin 12) and associated PCB ground plane for thermal and ground management."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Exposed pad (EP) is a special thermal/ground connection point listed in the datasheet as pin 33 but "+ ],+ "pages_sent": 18,+ "cost_usd": 0.3784,+ "at": "2026-09-22T09:56:44"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883532206231552",+ "pages": 18,+ "sha256": "fe3a860f8d3291fc",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}