component
ADM7154ARDZ-3.0-R7
Public Made by Adomby adom
Analog Devices Linear Voltage Regulators (LDO), SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownADM7154ARDZ-3.0-R7
Analog Devices · Linear Voltage Regulators (LDO) · SOIC-8-EP
ADM7154ARDZ-3.0-R7 from Analog Devices, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREG | power_in | Regulated input supply voltage to the LDO amplifier, to be bypassed to GND with a 10 µF or greater capacitor. |
| 2 | VOUT | power_out | Regulated output voltage, to be bypassed to GND with a 10 µF or greater capacitor. |
| 3 | BYP | passive | Low noise bypass capacitor pin; connect a 1 µF capacitor from BYP to GND to reduce noise and do not connect a load to it. |
| 4 | GND | power_in | Ground connection. |
| 5 | REF_SENSE | input | Reference sense; connect pin 5 to the REF pin and do not connect it to VOUT or GND. |
| 6 | REF | passive | Low noise reference voltage output, bypassed to GND with a 1 µF capacitor; short to REF_SENSE for fixed output voltages and do not connect a load to it. |
| 7 | EN | input | Enable input; drive high to turn the regulator on and low to turn it off, and connect to VIN for automatic startup. |
| 8 | VIN | power_in | Regulator input supply voltage, to be bypassed to GND with a 10 µF or greater capacitor. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8-EP |
| Category | Power Supply Chip |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.3 | 5.5 | V | 3 | ||
| Operating supply current | IGND | 4 | 7 | mA | ILOAD = 0 µA | 3 | |
| Operating supply current | IGND | 6.5 | 10 | mA | ILOAD = 600 mA | 3 | |
| Shutdown current | IIN_SD | 0.2 | 2 | µA | EN = GND | 3 | |
| Load current | ILOAD | 600 | mA | 3 | |||
| Initial accuracy | VOUT | -0.5 | 0.5 | % | ILOAD = 10 mA, TJ = +25°C | 3 | |
| Accuracy over line, load and temperature | VOUT | -2 | 1.5 | % | 1 mA < ILOAD < 600 mA, TJ = −40°C to +85°C | 3 | |
| Accuracy over load | VOUT | -2 | 2 | % | 1 mA < ILOAD < 600 mA | 3 | |
| Line regulation | ΔVOUT/ΔVIN | -0.02 | 0.02 | %/V | VIN = VOUT + 0.5 V or 2.3 V, whichever is greater, to 5.5 V | 3 | |
| Load regulation | ΔVOUT/ΔIOUT | 0.3 | 1.6 | %/A | IOUT = 1 mA to 600 mA | 3 | |
| Current-limit threshold | ILIMIT | 700 | 960 | 1200 | mA | VOUT | 3 |
| Dropout voltage | VDROPOUT | 80 | 130 | mV | IOUT = 400 mA, VOUT = 3.3 V | 3 | |
| Dropout voltage | VDROPOUT | 120 | 210 | mV | IOUT = 600 mA, VOUT = 3.3 V | 3 | |
| Precision EN logic high | ENHIGH | 1.13 | 1.22 | 1.31 | V | 2.3 V ≤ VIN ≤ 5.5 V | 4 |
| Precision EN logic low | ENLOW | 1.05 | 1.13 | 1.22 | V | 2.3 V ≤ VIN ≤ 5.5 V | 4 |
| Precision EN leakage current | IEN_LKG | 0.01 | 1 | µA | EN = VIN or GND | 4 | |
| Minimum input capacitance | CIN | 7 | µF | TA = −40°C to +125°C | 4 | ||
| Minimum regulator capacitance | CREG | 7 | µF | TA = −40°C to +125°C | 4 | ||
| Minimum output capacitance | COUT | 7 | µF | TA = −40°C to +125°C | 4 | ||
| Minimum bypass capacitance | CBYP | 0.1 | µF | TA = −40°C to +125°C | 4 | ||
| Minimum reference capacitance | CREF | 0.7 | µF | TA = −40°C to +125°C | 4 | ||
| Capacitor ESR (CREG, COUT, CIN, CREF) | RESR | 0.001 | 0.2 | Ω | TA = −40°C to +125°C | 4 | |
| Capacitor ESR (CBYP) | RESR | 0.001 | 2 | Ω | TA = −40°C to +125°C | 4 | |
| VIN to GND | VIN | -0.3 | 7 | V | 5 | ||
| VREG to GND | VREG | -0.3 | V | Maximum is VIN or +4 V, whichever is less | 5 | ||
| VOUT to GND | VOUT | -0.3 | V | Maximum is VREG or +4 V, whichever is less | 5 | ||
| BYP to VOUT | VBYP-VOUT | -0.3 | 0.3 | V | 5 | ||
| EN to GND | VEN | -0.3 | 7 | V | 5 | ||
| BYP to GND | VBYP | -0.3 | V | Maximum is VREG or +4 V, whichever is less | 5 | ||
| REF to GND | VREF | -0.3 | V | Maximum is VREG or +4 V, whichever is less | 5 | ||
| REF_SENSE to GND | VREF_SENSE | -0.3 | 4 | V | 5 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 5 | ||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Operating ambient temperature range | TA | -40 | 125 | °C | 5 | ||
| Output noise | OUTNOISE | 1.6 | µV rms | 10 Hz to 100 kHz, VOUT = 1.2 V to 3.3 V | 3 | ||
| Output noise | OUTNOISE | 0.9 | µV rms | 100 Hz to 100 kHz, VOUT = 1.2 V to 3.3 V | 3 | ||
| Noise spectral density | OUTNSD | 1.5 | nV/√Hz | 10 kHz to 1 MHz, VOUT = 1.2 V to 3.3 V | 3 | ||
| Power supply rejection ratio | PSRR | 90 | dB | 200 Hz to 200 kHz, VIN = 3.8 V, VOUT = 3.3 V, ILOAD = 400 mA | 3 | ||
| Power supply rejection ratio | PSRR | 58 | dB | 1 MHz, VIN = 3.8 V, VOUT = 3.3 V, ILOAD = 400 mA | 3 | ||
| VOUT pull-down resistance | VOUT_PULL | 550 | Ω | EN = 0 V, VOUT = 1 V, VIN = 5.5 V | 3 | ||
| REG pull-down resistance | VREG_PULL | 33 | kΩ | EN = 0 V, VREG = 1 V, VIN = 5.5 V | 3 | ||
| REF pull-down resistance | VREF_PULL | 620 | Ω | EN = 0 V, VREF = 1 V, VIN = 5.5 V | 3 | ||
| BYP pull-down resistance | VBYP_PULL | 400 | Ω | EN = 0 V, VBYP = 1 V, VIN = 5.5 V | 3 | ||
| VOUT start-up time | tSTARTUP | 1.2 | ms | VOUT = 3.3 V | 3 | ||
| VREG start-up time | tREG_STARTUP | 0.55 | ms | VOUT = 3.3 V | 3 | ||
| VREF start-up time | tREF_STARTUP | 0.44 | ms | VOUT = 3.3 V | 3 | ||
| Thermal shutdown threshold | TSSD | 150 | °C | TJ rising | 3 | ||
| Thermal shutdown hysteresis | TSSD_HYS | 15 | °C | 3 | |||
| Input UVLO rising threshold | UVLORISE | 2.29 | V | 3 | |||
| Input UVLO falling threshold | UVLOFALL | 1.95 | V | 3 | |||
| Input UVLO hysteresis | UVLOHYS | 200 | mV | 3 | |||
| VREG UVLO rising threshold | VREG_UVLORISE | 1.94 | V | 4 | |||
| VREG UVLO falling threshold | VREG_UVLOFALL | 1.6 | V | 4 | |||
| VREG UVLO hysteresis | VREG_UVLOHYS | 185 | mV | 4 | |||
| Precision EN hysteresis | ENHYS | 90 | mV | 4 | |||
| Junction-to-ambient thermal resistance (8-Lead SOIC) | θJA | 36.9 | °C/W | 8-Lead SOIC, 4-layer PCB | 5 | ||
| Junction-to-case thermal resistance (8-Lead SOIC) | θJC | 27.1 | °C/W | 8-Lead SOIC | 5 | ||
| Junction-to-board thermal characterization parameter (8-Lead SOIC) | ΨJB | 18.6 | °C/W | 8-Lead SOIC, 4-layer PCB | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | copper used to solder the package GND pin and exposed pad to | 19 |
CAD (KiCad official)
- Symbol:
ADM7154ARDZ-3.0-R7 - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
adm7154ardz-3-0-r7-etched.step/adm7154ardz-3-0-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adm7154ardz-3-0-r7.step/adm7154ardz-3-0-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (23 pp, sha256
d76fa82d6b9efff5, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).