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ADM691ANZ
Public Made by Adomby adom
Analog Devices Monitors & Reset Circuits, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADM691ANZ
Analog Devices · Monitors & Reset Circuits · PDIP-16
ADM691ANZ from Analog Devices, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBATT | power_in | Backup battery input; connect to an external battery or capacitor, or to ground if no backup battery is used. |
| 2 | VOUT | power_out | Output to which VCC or VBATT is internally switched, whichever is at the higher potential; supplies up to 250 mA from VCC, and connects to VCC if no backup battery is used. |
| 3 | VCC | power_in | Power supply input, +5 V. |
| 4 | GND | power_in | 0 V ground reference for all signals. |
| 5 | BATT ON | output | Logic output that goes high when VOUT is switched to VBATT and low when switched to VCC; can drive the base (via a resistor) of an external PNP transistor to raise output current above 250 mA. |
| 6 | LOW LINE | output | Logic output that goes low when VCC falls below the reset threshold and returns high as soon as VCC rises above it. |
| 7 | OSC IN | input | Oscillator logic input: with OSC SEL high or floating, low selects 100 ms and floating selects 1.6 s watchdog timeout; with OSC SEL low, it takes an external clock or a capacitor to GND to set reset and watchdog timing. |
| 8 | OSC SEL | input | Oscillator select input: floating or high enables the internal oscillator, low enables the external OSC IN; has a 10 µA internal pullup. |
| 9 | PFI | input | Noninverting power fail comparator input; PFO goes low when PFI is below 1.25 V; connect to GND or VOUT when not used. |
| 10 | PFO | output | Power fail comparator output that goes low when PFI is less than 1.25 V. |
| 11 | WDI | input | Three-level watchdog input: RESET pulses and WDO goes low if WDI stays high or low longer than the timeout; the watchdog is disabled if WDI is floating or driven to midsupply. |
| 12 | CEOUT | output | Chip enable output that goes low only when CEIN is low and VCC is above the reset threshold; if CEIN is low at reset it stays low for 15 µs or until CEIN goes high. |
| 13 | CEIN | input | Chip enable gating input; connect to GND or VOUT if not used. |
| 14 | WDO | output | Watchdog output that goes low if WDI stays high or low longer than the watchdog timeout, is set high by the next WDI transition, and stays high if WDI is unconnected. |
| 15 | RESET | output | Active-low logic reset output that goes low if VCC falls below the reset threshold and stays low for 200 ms typ after VCC rises above it. |
| 16 | RESET | output | Open-drain reset output that is the inverse of pin 15 RESET. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | PDIP-16 |
| Category | Power Supply Chip |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC, VBATT Operating Voltage Range | 0 | 5.5 | V | 2 | |||
| VCC to VOUT Output Resistance | 0.8 | 1.2 | Ω | VCC = 4.5 V | 2 | ||
| VBATT to VOUT Output Resistance (4.5 V) | 12 | Ω | VBATT = 4.5 V | 2 | |||
| VBATT to VOUT Output Resistance (2.8 V) | 20 | Ω | VBATT = 2.8 V | 2 | |||
| VBATT to VOUT Output Resistance (2.0 V) | 25 | Ω | VBATT = 2.0 V | 2 | |||
| Supply Current (Excludes IOUT) | 70 | 100 | µA | VCC > (VBATT, 1 V) | 2 | ||
| Supply Current in B. Backup (Excludes IOUT) | 0.04 | 1 | µA | VCC < (VBATT, 1.2 V), VBATT = 2.8 V | 2 | ||
| Battery Standby Current | -0.1 | 0.02 | µA | (VBATT +0.2 V) < VCC, TA = +25°C | 2 | ||
| Battery Standby Current (full temp) | -1 | 0.02 | µA | (VBATT +0.2 V) < VCC | 2 | ||
| Battery Switchover Hysteresis | 60 | mV | 2 | ||||
| BATT ON Output Voltage Low | 0.1 | 0.4 | V | ISINK = 3.2 mA | 2 | ||
| Reset Voltage Threshold ADM691A | 4.5 | 4.65 | 4.75 | V | ADM691A, ADM800L | 2 | |
| Reset Threshold Hysteresis | 15 | mV | 2 | ||||
| Reset Timeout Period Internal Oscillator | 140 | 200 | 280 | ms | Power Up | 2 | |
| Watchdog Timeout Period, Internal Oscillator (Long) | 1 | 1.6 | 2.25 | s | Long Period | 2 | |
| Watchdog Timeout Period, Internal Oscillator (Short) | 70 | 100 | 140 | ms | Short Period | 2 | |
| PFI Input Threshold ADM69xA | 1.2 | 1.25 | 1.3 | V | VCC = 5 V | 2 | |
| PFI Input Current | 0.01 | 25 | nA | 2 | |||
| CEIN Leakage Current | 0.005 | 1 | µA | Disable Mode | 3 | ||
| CEIN to CEOUT Resistance | 40 | 150 | Ω | Enable Mode | 3 | ||
| CEIN to CEOUT Propagation Delay | 6 | 10 | ns | RIN = 50 Ω, CLOAD = 50 pF | 3 | ||
| CEOUT Short-Circuit Current | 0.1 | 0.75 | 2 | mA | Disable Mode, CEOUT = 0 V | 3 | |
| VCC Supply Voltage | VCC | -0.3 | 6 | V | TA = 25°C | 3 | |
| VBATT Voltage | VBATT | -0.3 | 6 | V | TA = 25°C | 3 | |
| VCC Input Current (Peak) | 1000 | mA | 3 | ||||
| VCC Input Current (Continuous) | 250 | mA | 3 | ||||
| Power Dissipation, N-16 DIP | 842 | mW | 3 | ||||
| Thermal Impedance, N-16 DIP | θJA | 135 | °C/W | 3 | |||
| Operating Temperature Range | -40 | 85 | °C | Industrial (A Version) | 3 | ||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Lead Temperature (Soldering, 10 sec) | 300 | °C | 3 |
CAD (KiCad official)
- Symbol:
ADM691ANZ - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files:
adm691anz-etched.step/adm691anz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adm691anz.step/adm691anz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (12 pp, sha256
21aaacfd42c57a27, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADM691ANZ
**Analog Devices** · Monitors & Reset Circuits · PDIP-16
ADM691ANZ from Analog Devices, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBATT | power_in | Backup battery input; connect to an external battery or capacitor, or to ground if no backup battery is used. |
| 2 | VOUT | power_out | Output to which VCC or VBATT is internally switched, whichever is at the higher potential; supplies up to 250 mA from VCC, and connects to VCC if no backup battery is used. |
| 3 | VCC | power_in | Power supply input, +5 V. |
| 4 | GND | power_in | 0 V ground reference for all signals. |
| 5 | BATT ON | output | Logic output that goes high when VOUT is switched to VBATT and low when switched to VCC; can drive the base (via a resistor) of an external PNP transistor to raise output current above 250 mA. |
| 6 | LOW LINE | output | Logic output that goes low when VCC falls below the reset threshold and returns high as soon as VCC rises above it. |
| 7 | OSC IN | input | Oscillator logic input: with OSC SEL high or floating, low selects 100 ms and floating selects 1.6 s watchdog timeout; with OSC SEL low, it takes an external clock or a capacitor to GND to set reset and watchdog timing. |
| 8 | OSC SEL | input | Oscillator select input: floating or high enables the internal oscillator, low enables the external OSC IN; has a 10 µA internal pullup. |
| 9 | PFI | input | Noninverting power fail comparator input; PFO goes low when PFI is below 1.25 V; connect to GND or VOUT when not used. |
| 10 | PFO | output | Power fail comparator output that goes low when PFI is less than 1.25 V. |
| 11 | WDI | input | Three-level watchdog input: RESET pulses and WDO goes low if WDI stays high or low longer than the timeout; the watchdog is disabled if WDI is floating or driven to midsupply. |
| 12 | CEOUT | output | Chip enable output that goes low only when CEIN is low and VCC is above the reset threshold; if CEIN is low at reset it stays low for 15 µs or until CEIN goes high. |
| 13 | CEIN | input | Chip enable gating input; connect to GND or VOUT if not used. |
| 14 | WDO | output | Watchdog output that goes low if WDI stays high or low longer than the watchdog timeout, is set high by the next WDI transition, and stays high if WDI is unconnected. |
| 15 | RESET | output | Active-low logic reset output that goes low if VCC falls below the reset threshold and stays low for 200 ms typ after VCC rises above it. |
| 16 | RESET | output | Open-drain reset output that is the inverse of pin 15 RESET. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | PDIP-16 |
| Category | Power Supply Chip |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC, VBATT Operating Voltage Range | | 0 | | 5.5 | V | | 2 |
| VCC to VOUT Output Resistance | | | 0.8 | 1.2 | Ω | VCC = 4.5 V | 2 |
| VBATT to VOUT Output Resistance (4.5 V) | | | | 12 | Ω | VBATT = 4.5 V | 2 |
| VBATT to VOUT Output Resistance (2.8 V) | | | | 20 | Ω | VBATT = 2.8 V | 2 |
| VBATT to VOUT Output Resistance (2.0 V) | | | | 25 | Ω | VBATT = 2.0 V | 2 |
| Supply Current (Excludes IOUT) | | | 70 | 100 | µA | VCC > (VBATT, 1 V) | 2 |
| Supply Current in B. Backup (Excludes IOUT) | | | 0.04 | 1 | µA | VCC < (VBATT, 1.2 V), VBATT = 2.8 V | 2 |
| Battery Standby Current | | -0.1 | | 0.02 | µA | (VBATT +0.2 V) < VCC, TA = +25°C | 2 |
| Battery Standby Current (full temp) | | -1 | | 0.02 | µA | (VBATT +0.2 V) < VCC | 2 |
| Battery Switchover Hysteresis | | | 60 | | mV | | 2 |
| BATT ON Output Voltage Low | | | 0.1 | 0.4 | V | ISINK = 3.2 mA | 2 |
| Reset Voltage Threshold ADM691A | | 4.5 | 4.65 | 4.75 | V | ADM691A, ADM800L | 2 |
| Reset Threshold Hysteresis | | | 15 | | mV | | 2 |
| Reset Timeout Period Internal Oscillator | | 140 | 200 | 280 | ms | Power Up | 2 |
| Watchdog Timeout Period, Internal Oscillator (Long) | | 1 | 1.6 | 2.25 | s | Long Period | 2 |
| Watchdog Timeout Period, Internal Oscillator (Short) | | 70 | 100 | 140 | ms | Short Period | 2 |
| PFI Input Threshold ADM69xA | | 1.2 | 1.25 | 1.3 | V | VCC = 5 V | 2 |
| PFI Input Current | | | 0.01 | 25 | nA | | 2 |
| CEIN Leakage Current | | | 0.005 | 1 | µA | Disable Mode | 3 |
| CEIN to CEOUT Resistance | | | 40 | 150 | Ω | Enable Mode | 3 |
| CEIN to CEOUT Propagation Delay | | | 6 | 10 | ns | RIN = 50 Ω, CLOAD = 50 pF | 3 |
| CEOUT Short-Circuit Current | | 0.1 | 0.75 | 2 | mA | Disable Mode, CEOUT = 0 V | 3 |
| VCC Supply Voltage | VCC | -0.3 | | 6 | V | TA = 25°C | 3 |
| VBATT Voltage | VBATT | -0.3 | | 6 | V | TA = 25°C | 3 |
| VCC Input Current (Peak) | | | | 1000 | mA | | 3 |
| VCC Input Current (Continuous) | | | | 250 | mA | | 3 |
| Power Dissipation, N-16 DIP | | | | 842 | mW | | 3 |
| Thermal Impedance, N-16 DIP | θJA | | 135 | | °C/W | | 3 |
| Operating Temperature Range | | -40 | | 85 | °C | Industrial (A Version) | 3 |
| Storage Temperature Range | | -65 | | 150 | °C | | 3 |
| Lead Temperature (Soldering, 10 sec) | | | | 300 | °C | | 3 |
## CAD (KiCad official)
- Symbol: `ADM691ANZ`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files: `adm691anz-etched.step` / `adm691anz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adm691anz.step` / `adm691anz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADM691A_693A_800LM.pdf) (12 pp, sha256 `21aaacfd42c57a27`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adm691anz-datasheet.pdf)