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ADM3065ETRZ-EP

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Analog Devices RS-485/RS-422 ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232adm3065etrz-epfactory-2.0.0extractor-text

Verified ADM3065ETRZ-EP

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADM3065ETRZ-EP · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 18-page datasheet
  • ✓distributor: lcsc C658143, digikey 505-ADM3065ETRZ-EP-ND, mouser 584-ADM3065ETRZ-EP
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-g9_h78__/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.17)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ adm3065etrz-ep.kicad_sym✓ adm3065etrz-ep.kicad_mod✓ adm3065etrz-ep.step
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Ray Publish 0.1.0 b8af801 3d ago

ADM3065ETRZ-EP

Analog Devices · RS-485/RS-422 ICs · SOIC-8

ADM3065ETRZ-EP from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RO output Receiver output data, high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV, tristated when RE is driven high.
2 RE input Active-low receiver enable input; driving it low enables the receiver and driving it high disables the receiver.
3 DE input Driver enable; a high level enables the driver differential outputs A and B, a low level places the driver output into high impedance.
4 DI input Transmit data input; data to be transmitted by the driver is applied to this input.
5 GND power_in Ground.
6 A bidirectional Noninverting driver output and receiver input, put into high impedance when the driver is disabled or VCC is powered down.
7 B bidirectional Inverting driver output and receiver input, put into high impedance when the driver is disabled or VCC is powered down.
8 VCC power_in 3.0 V to 5.5 V power supply, with a 0.1 µF decoupling capacitor to GND recommended.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
No Load Supply Current ICC 2 7.5 mA DE = VIO, RE = 0 V 4
No Load Supply Current ICC 7.5 mA DE = VIO, RE = VIO 4
No Load Supply Current ICC 4.5 mA DE = 0 V, RE = 0 V 4
Supply Current, Data Rate = 50 Mbps ICC 107 172 mA VCC > 4.5 V, RL = 54 Ω, DE = VIO, RE = 0V 4
Supply Current, Data Rate = 50 Mbps ICC 67 75 mA RL = 54 Ω, DE = VIO, RE = 0 V (VCC = 3.0 V) 4
Supply Current in Shutdown Mode ISHDN 210 450 µA DE = 0 V, RE = VIO 4
Output Voltage, Loaded /VOD2/ 2 V VCC ≥ 3.0 V, RL = 50 Ω, see Figure 29 4
Output Voltage, Loaded /VOD2/ 1.5 V VCC ≥ 3.0 V, RL = 27 Ω (RS-485), see Figure 29 4
Output Voltage, Loaded /VOD2/ 2.1 V VCC ≥ 4.5 V, RL = 50 Ω, see Figure 29 4
Output Voltage over common-mode /VOD3/ 1.5 V VCC ≥ 3.0 V, −7 V ≤ VCM ≤ +12 V, see Figure 30 4
Output Voltage over common-mode /VOD3/ 2.1 V VCC ≥ 4.5 V, −7 V ≤ VCM ≤ +12 V, see Figure 30 4
Change in Differential Output Voltage ∆/VOD/ 0.2 V RL = 27 Ω or 50 Ω, see Figure 29 4
Common-Mode Output Voltage VOC 3 V RL = 27 Ω or 50 Ω, see Figure 29 4
Change in Common-Mode Voltage ∆/VOC/ 0.2 V RL = 27 Ω or 50 Ω, see Figure 29 4
Output Short-Circuit Current IOS -250 250 mA −7 V < VOUT < +12 V 4
Logic Input Voltage Low VIL 0.33 V DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V (0.33 × VIO) 4
Logic Input Voltage High VIH 0.67 V DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V (0.67 × VIO) 4
Logic Input Current II -2 2 µA DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V, 0 V ≤ VIN ≤ VIO 4
Differential Input Threshold Voltage VTH -200 -125 -30 mV −7 V < VCM < +12 V 4
Input Voltage Hysteresis VHYS 30 mV −7 V < VCM < +12 V 4
Receiver Input Current (A, B) II 0.25 mA DE = 0 V, VCC = powered/unpowered, VIN = 12 V 4
Receiver Input Current (A, B) II -0.2 mA DE = 0 V, VCC = powered/unpowered, VIN = −7 V 4
Line Input Resistance RIN 48 kΩ −7 V ≤ VCM ≤ +12 V 4
Receiver Output Voltage Low VOL 0.4 V VIO = 3.6 V, IOUT = 2 mA, VID ≤ −0.2 V 4
Receiver Output Voltage High VOH 2.4 V VIO = 3.0 V, IOUT = −2 mA, VID ≥ −0.03 V 5
Receiver Short-Circuit Current 85 mA VOUT = GND or VIO 5
Three-State Output Leakage IOZR -2 2 µA RO = 0 V or VIO 5
Driver Maximum Data Rate 50 Mbps 5
Driver Propagation Delay tDPLH, tDPHL 9 15 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 4 and Figure 31 5
Driver Skew tDSKEW 1 2 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 4 and Figure 31 5
Driver Rise/Fall Times tDR, tDF 4 6.7 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 4 and Figure 31 5
Driver Enable to Output High tDZH 10 30 ns RL = 110 Ω, CL = 50 pF, see Figure 5 and Figure 32 5
Driver Enable to Output Low tDZL 10 30 ns RL = 110 Ω, CL = 50 pF, see Figure 5 and Figure 32 5
Driver Disable Time from Low tDLZ 10 30 ns RL = 110 Ω, CL = 50 pF, see Figure 5 and Figure 32 5
Driver Disable Time from High tDHZ 10 30 ns RL = 110 Ω, CL = 50 pF, see Figure 5 and Figure 32 5
Driver Enable Time from Shutdown to High tDZH(SHDN) 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 5 and Figure 32 5
Driver Enable Time from Shutdown to Low tDZL(SHDN) 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 5 and Figure 32 5
Receiver Maximum Data Rate 50 Mbps 5
Receiver Propagation Delay tRPLH, tRPHL 35 ns CL = 15 pF, /VID/ ≥ 1.5 V, VCM = 1.5 V, see Figure 6 and Figure 33 5
Receiver Skew/Pulse Width Distortion tRSKEW 3.5 ns CL = 15 pF, /VID/ ≥ 1.5 V, VCM = 1.5 V, see Figure 6 and Figure 33 5
Receiver Enable to Output High tRZH 10 35 ns RL = 1 kΩ, CL = 15 pF, /VID/ ≥ 1.5 V, DE high, see Figure 7 and Figure 35 5
Receiver Enable to Output Low tRZL 10 35 ns RL = 1 kΩ, CL = 15 pF, /VID/ ≥ 1.5 V, DE high, see Figure 7 and Figure 35 5
Receiver Disable Time from Low tRLZ 10 35 ns RL = 1 kΩ, CL = 15 pF, /VID/ ≥ 1.5 V, see Figure 7 and Figure 35 5
Receiver Disable Time from High tRHZ 10 35 ns RL = 1 kΩ, CL = 15 pF, /VID/ ≥ 1.5 V, see Figure 7 and Figure 35 5
Receiver Enable from Shutdown to High tRZH(SHDN) 2000 ns RL = 1 kΩ, CL = 15 pF, /VID/ ≥ 1.5 V, see Figure 7 and Figure 34 5
Receiver Enable from Shutdown to Low tRZL(SHDN) 2000 ns RL = 1 kΩ, CL = 15 pF, /VID/ ≥ 1.5 V, see Figure 7 and Figure 34 5
Time to Shutdown tSHDN 40 ns 5
VCC to GND VCC 6 V 8
VIO to GND VIO -0.3 6 V 8
Digital Input and Output Voltage (DE, RE, DI, RO) -0.3 V max is VCC + 0.3 V 8
Driver Output and Receiver Input Voltage -9 14 V 8
Operating Temperature Range -55 125 °C 8
Storage Temperature Range -65 150 °C 8
Continuous Total Power Dissipation, 8-Lead SOIC_N 0.225 W 8-Lead SOIC_N 8
Maximum Junction Temperature TJ 150 °C 8
Thermal Resistance Junction to Ambient θJA 110.88 °C/W R-8, JEDEC 2S2P simulated 8
Thermal Resistance Junction to Case θJC 58.63 °C/W R-8, JEDEC 2S2P simulated 8

CAD (KiCad official)

  • Symbol: ADM3065ETRZ-EP
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: adm3065etrz-ep-etched.step / adm3065etrz-ep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adm3065etrz-ep.step / adm3065etrz-ep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (18 pp, sha256 576e8e061709aa21, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF