Analog Devices , LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADM1281-1ACPZ

Analog Devices · IC · LFCSP-32(5x5)

ADM1281-1ACPZ from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PSET	input	Programs the constant power limit, with FET power limited to (VPSET × 8)/(50 × RSENSE), and it can be set by a resistor divider from VCAP or an external reference.
2	VCAP	power_out	Internal regulated supply that requires a capacitor of 1 µF or greater for accuracy and can be used as the reference for the ISET pin, regulated at 2.68 V to 2.72 V.
3	ISET	input	Programs the current-limit threshold, with the default limit set by connecting it directly to VCAP and a recommended operating range of 0.25 V to 1.25 V for 5 mV to 25 mV VSENSE current limits.
4	ISTART	input	Sets the start-up current limit for dv/dt power-up, active only while PWRGD is low, with an active range of 0.1 V to 1.25 V and tied to VCAP to disable the start-up limit.
5	TIMER	passive	An external capacitor sets the initial power-on delay and overcurrent fault delay, and GATE is pulled low when TIMER exceeds its 1.0 V high threshold.
6	FAULT	output	Open-drain output that asserts low and latches after an overcurrent fault, overtemperature fault, or FET health fault, with a low output of 0.4 V at 1 mA.
7	ADR1	input	PMBus address select pin that can be connected to GND, connected to VCAP, left floating, or connected low through a 150 kΩ resistor, which together with ADR2 selects one of 16 addresses.
8	ADR2	input	PMBus address select pin that can be connected to GND, connected to VCAP, left floating, or connected low through a 150 kΩ resistor, which together with ADR1 selects one of 16 addresses.
9	DNC	unconnected	Do not connect.
10	DNC	unconnected	Do not connect.
11	DNC	unconnected	Do not connect.
12	ENABLE	input	On the ADM1281-1 this active-high input must be high to allow a power-up sequence, with VIH of 1.1 V minimum, VIL of 0.8 V maximum, and a 1 µs glitch filter.
13	GPO1/ALERT1/CONV	bidirectional	Configurable as a general-purpose digital output, an open-drain alert output that is the default at power-up, or a CONV input that controls when a power monitor ADC sampling cycle begins.
14	GPO2/ALERT2	output	Configurable as a general-purpose digital output or an open-drain alert output that is the default at power-up, with a low output of 0.4 V at 1 mA.
15	SDA	bidirectional	Open-drain serial data input/output that requires an external pull-up resistor, with VIH of 1.1 V minimum and VIL of 0.8 V maximum, and should be tied to GND or a pull-up if unused.
16	SCL	input	Open-drain serial clock input that requires an external pull-up resistor, and should be tied to GND or a pull-up to VCAP or another supply if unused.
17	RETRY	input	Has an internal 8 µA pull-up that enables the default latch-off mode after an overcurrent fault, and pulling it low enables a 10 second automatic retry.
18	PWRGD	output	Open-drain power-good output that indicates the supply is within tolerance, no faults are detected, and the gate is fully enhanced, with a valid output guaranteed at VCC of 1 V.
19	CSOUT	output	Outputs the VSENSE_HS voltage amplified by a gain of 350 V/V to represent load current, with total output error of ±1.6% at VSENSE_HS = 20 mV.
20	VOUT	input	Input used to read back the output voltage through the internal ADC via a 1 kΩ series resistor from the FET source, and also used with HS− to calculate FET drain-to-source voltage for constant power foldback.
21	PWGIN	input	Sets the power-good threshold with a 1.0 V falling threshold and 60 mV typical hysteresis, using a resistor divider from the FET source (VOUT), and PWRGD is not asserted until the output is above this threshold.
22	GND	power_in	Ground connection for all sensitive analog nodes that should be isolated in a ground island and connected to the main ground plane at a single point as close to the pin as possible.
23	PGND	power_in	Return path for the strong gate pull-down current and for the external transistor used for temperature measurement.
24	GATE	output	High-side gate drive for an external N-channel FET, driven by a charge pump to regulate maximum load current, clamped to ≤31 V, and held low when VCC is below UVLO.
25	TEMP	passive	Connects to an external NPN transistor placed near the MOSFETs for remote temperature sensing, with the voltage measured by the internal ADC and an operating range of −55 °C to +150 °C limited by the external diode.
26	MO−	input	Negative power monitor input where a sense resistor between MO+ and MO− sets the sense voltage for load current measurement, with the power monitor amplifier input range of ±25 mV.
27	HS−	input	Negative current sense input where a sense resistor between HS+ and HS− sets the analog current limit, and the hot-swap loop maintains VHS+ − VHS− at that sense voltage.
28	HS+	input	Positive current sense input connected to the main supply, which together with HS− sets the analog current limit and is also used by the ADC to measure input voltage, with specifications given for VHS+ from 4 V to 20 V.
29	MO+	input	Positive power monitor input where a sense resistor between MO+ and MO− sets the sense voltage used by the ADC to measure load current, with the power monitor amplifier input range of ±25 mV.
30	VCC	power_in	Positive supply input with an operating voltage range of 4.5 V to 20 V and UVLO of 2.4 V to 2.7 V, recommended to be greater than or equal to HS+ and MO+ during normal operation.
31	UV	input	Undervoltage input set by an external resistor divider, with a 1.0 V falling threshold, 60 mV typical hysteresis, and an absolute maximum rating of −0.3 V to +4 V.
32	OV	input	Overvoltage input set by an external resistor divider, with a 1.0 V rising threshold, 60 mV typical hysteresis, and an absolute maximum rating of −0.3 V to +4 V.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-32(5x5)
Category
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Quiescent Current	ICC			5.5	mA	GATE on and power monitor running	4
Undervoltage Lockout	UVLO	2.4		2.7	V	VCC rising	4
UV Threshold	UVTH	0.99	1	1.01	V	UV falling	4
OV Threshold	OVTH	0.99	1	1.01	V	OV rising	4
GATE Pull-Down Current Fast	IGATEDN_FAST	1500	2400	3000	mA	VGATE ≥ 12 V; VCC ≥ 12 V	4
GATE Pull-Down Current Slow	IGATEDN_SLOW	5	10	15	mA	VGATE ≥ 2 V	4
GATE Pull-Down Current Regulation	IGATEDN_REG	45	60	75	μA	VGATE ≥ 2 V; VISET = 1.0 V; (VHS+ − VHS−) = 30 mV	4
GATE Pull-Up Current	IGATEUP	-30		-20	μA	VGATE = 0 V	4
GATE Drive Voltage	ΔVGATE	10	12	14	V	20 V ≥ VCC ≥ 8 V; IGATE ≤ 5 μA	4
Hot-Swap Sense Voltage Current Limit	VSENSECL	19.75	20	20.25	mV	VISET > 1.65 V; VGATE = (VHS+ + 3 V); IGATE = 0 μA	4
Hot-Swap Sense Voltage Constant Power Inactive	VSENSECL	24.75	25	25.25	mV	VISET = 1.25 V; VDS < 2 V	4
Severe Overcurrent Voltage Threshold (225%, default at power-up)	VSENSEOC	43	45	47	mV	VISET > 1.65 V; VPSET > 1.1 V; default at power-up (225%)	5
Severe Overcurrent Voltage Threshold (125%)	VSENSEOC	23	25	27	mV	VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (125%)	5
TIMER Pull-Up Current Overcurrent Fault	ITIMERUPFLT	-63	-60	-57	μA	Overcurrent fault; 0.2 V ≤ VTIMER ≤ 1 V	5
TIMER Pull-Up Current Power-On Reset	ITIMERUPPOR	-4	-3	-2	μA	Initial power-on reset; VTIMER = 0.5 V	5
TIMER Pull-Down Current Retry	ITIMERDNRT	1.7	2	2.3	μA	After fault when GATE is off; VTIMER = 0.5 V	5
TIMER High Threshold	VTIMERH	0.98	1	1.02	V		5
TIMER Low Threshold	VTIMERL	0.18	0.2	0.22	V		5
ENABLE Pin Input High Voltage	VIH	1.1			V		6
ENABLE Pin Input Low Voltage	VIL			0.8	V		6
FAULT Pin Output Low Voltage	VOL_LATCH			0.4	V	IFAULT = 1 mA	5
CSOUT Total Output Error		-1.6		1.6	%	VSENSE_HS = 20 mV; ICSOUT ≤ 1 mA; CCSOUT = 1 nF	6
PWGIN Threshold	PWGINTH	0.99	1	1.01	V	PWGIN falling	6
ADC Conversion Time, One Sample of IOUT		144		165	μs	One sample of IOUT; from command received to valid data in register	6
Input Current for Address Set to 00		-40		-22	μA	VADRx = 0 V to 0.8 V	7
SDA, SCL Input High Voltage	VIH	1.1			V		7
SDA, SCL Input Low Voltage	VIL			0.8	V		7
SDA, SCL Input Leakage	ILEAK-PIN	-10		10	μA		7
Nominal Bus Voltage	VDD	2.7		5.5	V	3 V to 5 V ± 10%	7
MO+ and MO− Input Current	IMO±			60	nA	Per individual pin; VMO+, VMO− = 19.6 V	4
HS+ and HS− Input Imbalance	IΔSENSE			8	μA	IΔSENSE = (I+ − I−)	4
HS+ and HS− Input Current	ISENSEx			150	μA	Per individual pin; VHS+, VHS− = 20 V	4
Internally Regulated Voltage	VVCAP	2.68	2.7	2.72	V	0 µA ≤ IVCAP ≤ 100 µA; CVCAP = 1 μF	4
Current Sense Absolute Error (A grade, 128-sample averaging)		-0.7	0.04	0.7	%	VCC = 4.5 V to 15 V; VMO+ = 4 V to 15 V; VSENSE_MO = 20 mV; 128-sample averaging	8
Operating Voltage Range	VCC	4.5		20	V		4
HS+ Operating Voltage	VHS+	4		20	V	VCC ≥ VHS+ and VMO+	4
Recommended Maximum Operating Range (current-limit reference)	VISET	0.25		1.25	V	5 mV to 25 mV VSENSE current limit	4
VCC Pin	VCC	-0.3		25	V		10
UV Pin	UV	-0.3		4	V		10
OV Pin	OV	-0.3		4	V		10
ISET Pin	ISET	-0.3		4	V		10
PSET Pin	PSET	-0.3		4	V		10
VCAP Pin	VCAP	-0.3		4	V		10
HS+ Pin	HS+	-0.3		25	V		10
HS− Pin	HS−	-0.3		25	V		10
Sense Voltage (VHS+ − VHS−)	VSENSE_HS	-0.3		0.3	V		10
FAULT Pin	FAULT	-0.3		25	V		10
ENABLE Pin	ENABLE	-0.3		25	V		10
PWRGD Pin	PWRGD	-0.3		25	V		10
VOUT Pin	VOUT	-0.3		25	V		10
GATE Pin (Internal Supply Only)	GATE	-0.3		36	V		10
SCL Pin	SCL	-0.3		6.5	V		10
SDA Pin	SDA	-0.3		6.5	V		10
Continuous Current into Any Pin		-10		10	mA		10
Storage Range		-65		125	°C		10
Operating Range		-40		85	°C		10
Junction Temperature				105	°C		10
Lead Soldering (10 sec)				300	°C	10 s	10
Thermal Resistance, Junction-to-Ambient (CP-32-20)	θJA		32.5		°C/W	Natural convection, one cubic foot sealed enclosure	10

CAD (KiCad official)

Symbol: ADM1281-1ACPZ
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
3D model files: adm1281-1acpz-etched.step / adm1281-1acpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adm1281-1acpz.step / adm1281-1acpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (63 pp, sha256 c234b2963102a5db, retrieved 2026-11-04, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# ADM1281-1ACPZ

**Analog Devices** · IC · LFCSP-32(5x5)

ADM1281-1ACPZ from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PSET | input | Programs the constant power limit, with FET power limited to (VPSET × 8)/(50 × RSENSE), and it can be set by a resistor divider from VCAP or an external reference. |
| 2 | VCAP | power_out | Internal regulated supply that requires a capacitor of 1 µF or greater for accuracy and can be used as the reference for the ISET pin, regulated at 2.68 V to 2.72 V. |
| 3 | ISET | input | Programs the current-limit threshold, with the default limit set by connecting it directly to VCAP and a recommended operating range of 0.25 V to 1.25 V for 5 mV to 25 mV VSENSE current limits. |
| 4 | ISTART | input | Sets the start-up current limit for dv/dt power-up, active only while PWRGD is low, with an active range of 0.1 V to 1.25 V and tied to VCAP to disable the start-up limit. |
| 5 | TIMER | passive | An external capacitor sets the initial power-on delay and overcurrent fault delay, and GATE is pulled low when TIMER exceeds its 1.0 V high threshold. |
| 6 | FAULT | output | Open-drain output that asserts low and latches after an overcurrent fault, overtemperature fault, or FET health fault, with a low output of 0.4 V at 1 mA. |
| 7 | ADR1 | input | PMBus address select pin that can be connected to GND, connected to VCAP, left floating, or connected low through a 150 kΩ resistor, which together with ADR2 selects one of 16 addresses. |
| 8 | ADR2 | input | PMBus address select pin that can be connected to GND, connected to VCAP, left floating, or connected low through a 150 kΩ resistor, which together with ADR1 selects one of 16 addresses. |
| 9 | DNC | unconnected | Do not connect. |
| 10 | DNC | unconnected | Do not connect. |
| 11 | DNC | unconnected | Do not connect. |
| 12 | ENABLE | input | On the ADM1281-1 this active-high input must be high to allow a power-up sequence, with VIH of 1.1 V minimum, VIL of 0.8 V maximum, and a 1 µs glitch filter. |
| 13 | GPO1/ALERT1/CONV | bidirectional | Configurable as a general-purpose digital output, an open-drain alert output that is the default at power-up, or a CONV input that controls when a power monitor ADC sampling cycle begins. |
| 14 | GPO2/ALERT2 | output | Configurable as a general-purpose digital output or an open-drain alert output that is the default at power-up, with a low output of 0.4 V at 1 mA. |
| 15 | SDA | bidirectional | Open-drain serial data input/output that requires an external pull-up resistor, with VIH of 1.1 V minimum and VIL of 0.8 V maximum, and should be tied to GND or a pull-up if unused. |
| 16 | SCL | input | Open-drain serial clock input that requires an external pull-up resistor, and should be tied to GND or a pull-up to VCAP or another supply if unused. |
| 17 | RETRY | input | Has an internal 8 µA pull-up that enables the default latch-off mode after an overcurrent fault, and pulling it low enables a 10 second automatic retry. |
| 18 | PWRGD | output | Open-drain power-good output that indicates the supply is within tolerance, no faults are detected, and the gate is fully enhanced, with a valid output guaranteed at VCC of 1 V. |
| 19 | CSOUT | output | Outputs the VSENSE_HS voltage amplified by a gain of 350 V/V to represent load current, with total output error of ±1.6% at VSENSE_HS = 20 mV. |
| 20 | VOUT | input | Input used to read back the output voltage through the internal ADC via a 1 kΩ series resistor from the FET source, and also used with HS− to calculate FET drain-to-source voltage for constant power foldback. |
| 21 | PWGIN | input | Sets the power-good threshold with a 1.0 V falling threshold and 60 mV typical hysteresis, using a resistor divider from the FET source (VOUT), and PWRGD is not asserted until the output is above this threshold. |
| 22 | GND | power_in | Ground connection for all sensitive analog nodes that should be isolated in a ground island and connected to the main ground plane at a single point as close to the pin as possible. |
| 23 | PGND | power_in | Return path for the strong gate pull-down current and for the external transistor used for temperature measurement. |
| 24 | GATE | output | High-side gate drive for an external N-channel FET, driven by a charge pump to regulate maximum load current, clamped to ≤31 V, and held low when VCC is below UVLO. |
| 25 | TEMP | passive | Connects to an external NPN transistor placed near the MOSFETs for remote temperature sensing, with the voltage measured by the internal ADC and an operating range of −55 °C to +150 °C limited by the external diode. |
| 26 | MO− | input | Negative power monitor input where a sense resistor between MO+ and MO− sets the sense voltage for load current measurement, with the power monitor amplifier input range of ±25 mV. |
| 27 | HS− | input | Negative current sense input where a sense resistor between HS+ and HS− sets the analog current limit, and the hot-swap loop maintains VHS+ − VHS− at that sense voltage. |
| 28 | HS+ | input | Positive current sense input connected to the main supply, which together with HS− sets the analog current limit and is also used by the ADC to measure input voltage, with specifications given for VHS+ from 4 V to 20 V. |
| 29 | MO+ | input | Positive power monitor input where a sense resistor between MO+ and MO− sets the sense voltage used by the ADC to measure load current, with the power monitor amplifier input range of ±25 mV. |
| 30 | VCC | power_in | Positive supply input with an operating voltage range of 4.5 V to 20 V and UVLO of 2.4 V to 2.7 V, recommended to be greater than or equal to HS+ and MO+ during normal operation. |
| 31 | UV | input | Undervoltage input set by an external resistor divider, with a 1.0 V falling threshold, 60 mV typical hysteresis, and an absolute maximum rating of −0.3 V to +4 V. |
| 32 | OV | input | Overvoltage input set by an external resistor divider, with a 1.0 V rising threshold, 60 mV typical hysteresis, and an absolute maximum rating of −0.3 V to +4 V. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-32(5x5) |
| Category |  |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Quiescent Current | ICC |  |  | 5.5 | mA | GATE on and power monitor running | 4 |
| Undervoltage Lockout | UVLO | 2.4 |  | 2.7 | V | VCC rising | 4 |
| UV Threshold | UVTH | 0.99 | 1 | 1.01 | V | UV falling | 4 |
| OV Threshold | OVTH | 0.99 | 1 | 1.01 | V | OV rising | 4 |
| GATE Pull-Down Current Fast | IGATEDN_FAST | 1500 | 2400 | 3000 | mA | VGATE ≥ 12 V; VCC ≥ 12 V | 4 |
| GATE Pull-Down Current Slow | IGATEDN_SLOW | 5 | 10 | 15 | mA | VGATE ≥ 2 V | 4 |
| GATE Pull-Down Current Regulation | IGATEDN_REG | 45 | 60 | 75 | μA | VGATE ≥ 2 V; VISET = 1.0 V; (VHS+ − VHS−) = 30 mV | 4 |
| GATE Pull-Up Current | IGATEUP | -30 |  | -20 | μA | VGATE = 0 V | 4 |
| GATE Drive Voltage | ΔVGATE | 10 | 12 | 14 | V | 20 V ≥ VCC ≥ 8 V; IGATE ≤ 5 μA | 4 |
| Hot-Swap Sense Voltage Current Limit | VSENSECL | 19.75 | 20 | 20.25 | mV | VISET > 1.65 V; VGATE = (VHS+ + 3 V); IGATE = 0 μA | 4 |
| Hot-Swap Sense Voltage Constant Power Inactive | VSENSECL | 24.75 | 25 | 25.25 | mV | VISET = 1.25 V; VDS < 2 V | 4 |
| Severe Overcurrent Voltage Threshold (225%, default at power-up) | VSENSEOC | 43 | 45 | 47 | mV | VISET > 1.65 V; VPSET > 1.1 V; default at power-up (225%) | 5 |
| Severe Overcurrent Voltage Threshold (125%) | VSENSEOC | 23 | 25 | 27 | mV | VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (125%) | 5 |
| TIMER Pull-Up Current Overcurrent Fault | ITIMERUPFLT | -63 | -60 | -57 | μA | Overcurrent fault; 0.2 V ≤ VTIMER ≤ 1 V | 5 |
| TIMER Pull-Up Current Power-On Reset | ITIMERUPPOR | -4 | -3 | -2 | μA | Initial power-on reset; VTIMER = 0.5 V | 5 |
| TIMER Pull-Down Current Retry | ITIMERDNRT | 1.7 | 2 | 2.3 | μA | After fault when GATE is off; VTIMER = 0.5 V | 5 |
| TIMER High Threshold | VTIMERH | 0.98 | 1 | 1.02 | V |  | 5 |
| TIMER Low Threshold | VTIMERL | 0.18 | 0.2 | 0.22 | V |  | 5 |
| ENABLE Pin Input High Voltage | VIH | 1.1 |  |  | V |  | 6 |
| ENABLE Pin Input Low Voltage | VIL |  |  | 0.8 | V |  | 6 |
| FAULT Pin Output Low Voltage | VOL_LATCH |  |  | 0.4 | V | IFAULT = 1 mA | 5 |
| CSOUT Total Output Error |  | -1.6 |  | 1.6 | % | VSENSE_HS = 20 mV; ICSOUT ≤ 1 mA; CCSOUT = 1 nF | 6 |
| PWGIN Threshold | PWGINTH | 0.99 | 1 | 1.01 | V | PWGIN falling | 6 |
| ADC Conversion Time, One Sample of IOUT |  | 144 |  | 165 | μs | One sample of IOUT; from command received to valid data in register | 6 |
| Input Current for Address Set to 00 |  | -40 |  | -22 | μA | VADRx = 0 V to 0.8 V | 7 |
| SDA, SCL Input High Voltage | VIH | 1.1 |  |  | V |  | 7 |
| SDA, SCL Input Low Voltage | VIL |  |  | 0.8 | V |  | 7 |
| SDA, SCL Input Leakage | ILEAK-PIN | -10 |  | 10 | μA |  | 7 |
| Nominal Bus Voltage | VDD | 2.7 |  | 5.5 | V | 3 V to 5 V ± 10% | 7 |
| MO+ and MO− Input Current | IMO± |  |  | 60 | nA | Per individual pin; VMO+, VMO− = 19.6 V | 4 |
| HS+ and HS− Input Imbalance | IΔSENSE |  |  | 8 | μA | IΔSENSE = (I+ − I−) | 4 |
| HS+ and HS− Input Current | ISENSEx |  |  | 150 | μA | Per individual pin; VHS+, VHS− = 20 V | 4 |
| Internally Regulated Voltage | VVCAP | 2.68 | 2.7 | 2.72 | V | 0 µA ≤ IVCAP ≤ 100 µA; CVCAP = 1 μF | 4 |
| Current Sense Absolute Error (A grade, 128-sample averaging) |  | -0.7 | 0.04 | 0.7 | % | VCC = 4.5 V to 15 V; VMO+ = 4 V to 15 V; VSENSE_MO = 20 mV; 128-sample averaging | 8 |
| Operating Voltage Range | VCC | 4.5 |  | 20 | V |  | 4 |
| HS+ Operating Voltage | VHS+ | 4 |  | 20 | V | VCC ≥ VHS+ and VMO+ | 4 |
| Recommended Maximum Operating Range (current-limit reference) | VISET | 0.25 |  | 1.25 | V | 5 mV to 25 mV VSENSE current limit | 4 |
| VCC Pin | VCC | -0.3 |  | 25 | V |  | 10 |
| UV Pin | UV | -0.3 |  | 4 | V |  | 10 |
| OV Pin | OV | -0.3 |  | 4 | V |  | 10 |
| ISET Pin | ISET | -0.3 |  | 4 | V |  | 10 |
| PSET Pin | PSET | -0.3 |  | 4 | V |  | 10 |
| VCAP Pin | VCAP | -0.3 |  | 4 | V |  | 10 |
| HS+ Pin | HS+ | -0.3 |  | 25 | V |  | 10 |
| HS− Pin | HS− | -0.3 |  | 25 | V |  | 10 |
| Sense Voltage (VHS+ − VHS−) | VSENSE_HS | -0.3 |  | 0.3 | V |  | 10 |
| FAULT Pin | FAULT | -0.3 |  | 25 | V |  | 10 |
| ENABLE Pin | ENABLE | -0.3 |  | 25 | V |  | 10 |
| PWRGD Pin | PWRGD | -0.3 |  | 25 | V |  | 10 |
| VOUT Pin | VOUT | -0.3 |  | 25 | V |  | 10 |
| GATE Pin (Internal Supply Only) | GATE | -0.3 |  | 36 | V |  | 10 |
| SCL Pin | SCL | -0.3 |  | 6.5 | V |  | 10 |
| SDA Pin | SDA | -0.3 |  | 6.5 | V |  | 10 |
| Continuous Current into Any Pin |  | -10 |  | 10 | mA |  | 10 |
| Storage Range |  | -65 |  | 125 | °C |  | 10 |
| Operating Range |  | -40 |  | 85 | °C |  | 10 |
| Junction Temperature |  |  |  | 105 | °C |  | 10 |
| Lead Soldering (10 sec) |  |  |  | 300 | °C | 10 s | 10 |
| Thermal Resistance, Junction-to-Ambient (CP-32-20) | θJA |  | 32.5 |  | °C/W | Natural convection, one cubic foot sealed enclosure | 10 |

## CAD (KiCad official)

- Symbol: `ADM1281-1ACPZ`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
- 3D model files: `adm1281-1acpz-etched.step` / `adm1281-1acpz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adm1281-1acpz.step` / `adm1281-1acpz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/adm1281.pdf) (63 pp, sha256 `c234b2963102a5db`, retrieved 2026-11-04, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/adm1281-1acpz-datasheet.pdf)

ADM1281-1ACPZ

Verified ADM1281-1ACPZ

Verification log 1 record

ADM1281-1ACPZ

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance