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ADM1278-1ACPZ-RL

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Analog Devices Surge Protection Devices (SPDs), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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ADM1278-1ACPZ-RL

Analog Devices · Surge Protection Devices (SPDs) · LFCSP-32(5x5)

ADM1278-1ACPZ-RL from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PSET input Power limit programming pin; FET power limit = (VPSET × 8)/(50 × RSENSE) with reference threshold 1.35 to 1.65 V when compared to 2.7 V internal reference.
2 VCAP power_in Internal regulated supply output 2.68 to 2.72 V (A/AA grade) or 2.66 to 2.74 V (B grade), requires 1 μF or greater capacitor, with maximum load 100 μA for accuracy.
3 ISET input Current limit threshold programmable via resistor divider from VCAP for 5 to 25 mV sense voltage, with internal 1 V reference when VISET exceeds 1.5 V threshold.
4 ISTART input Start-up current limit input for dv/dt power-up mode, active only while PWRGD is low, with reference threshold 1.35 to 1.65 V for mode selection.
5 TIMER input Timer capacitor pin for setting initial insertion delay (minimum 27 ms) and fault regulation time, with thresholds 0.2 V and 1.0 V, pull-up currents 3 and 60 μA, pull-down currents 2 and 100 μA.
6 FAULT tri_state Open-drain latched fault output asserts low upon overcurrent timeout, overtemperature, or FET health fault detection, with VOL maximum 0.4 V at 1 mA.
7 ADR1 input PMBus address decode pin; can be tied to GND (low), VCAP (high), left floating (high-Z), or 150 kΩ to GND (resistor) for 16 unique device addresses.
8 ADR2 input PMBus address decode pin; can be tied to GND (low), VCAP (high), left floating (high-Z), or 150 kΩ to GND (resistor) for 16 unique device addresses.
9 NIC unconnected Not internally connected.
10 NIC unconnected Not internally connected.
11 NIC unconnected Not internally connected.
12 ENABLE input Active high digital input with VIH 1.1 V and VIL 0.8 V; must be high to allow hot swap controller power-up sequence with 1 μs glitch filter.
13 GPO1/ALERT1/CONV tri_state Open-drain output configurable as general-purpose output, alert signal, or conversion input, defaults to alert output at power-up with VOL maximum 0.4 V at 1 mA.
14 GPO2/ALERT2 tri_state Open-drain output configurable as general-purpose output or alert signal, defaults to alert output at power-up with VOL maximum 0.4 V at 1 mA.
15 SDA bidirectional Open-drain serial data input/output for PMBus interface, requires external pull-up resistor, with VIH 1.1 V and VIL 0.8 V input thresholds.
16 SCL input Open-drain serial clock input for PMBus interface, requires external pull-up resistor, with VIH 1.1 V and VIL 0.8 V input thresholds.
17 RETRY input Retry mode selection pin with internal 8 μA pull-up; floating enables latch-off mode after overcurrent fault, pulling low enables 10 second automatic retry.
18 PWRGD tri_state Open-drain power-good signal output asserts high when output voltage above threshold, no faults active, hot swap enabled, and MOSFET fully enhanced, with VOL maximum 0.4 V at 1 mA.
19 CSOUT output Current sense amplifier output with 350 V/V gain (CSOUT = VSENSE_HS × 350), short-circuit current limited to 5 mA, with ±1.6% total output error at 20 mV sense.
20 VOUT input Output voltage measurement input via 1 kΩ series resistor to FET source; used by 12-bit ADC for voltage monitoring and by constant power foldback for VDS calculation.
21 PWGIN input Power-good threshold input pin; comparator threshold 1.0 V with 50 to 70 mV hysteresis, input current 50 nA at voltages ≤3.6 V.
22 GND power_in Analog ground connection for sensitive nodes; must be isolated from main high current path and connected to main ground plane at single point.
23 PGND power_in Power ground return path for 1500 mA maximum gate pull-down current and external temperature sensing transistor.
24 GATE output High-side gate drive output for external N-channel FET, clamped to maximum 31 V and 14 V above HS± pins, with 10 to 14 V drive voltage at 5 μA load.
25 TEMP input Remote temperature sensing input for external NPN/PNP transistor measurement via internal 12-bit ADC, with 0.25 °C resolution and ±1 to ±10 °C accuracy.
26 MO− input Negative power monitor current sense input for 50 V/V amplifier with ±25 mV input range, input current 25 nA maximum at 20 V.
27 HS− input Negative hot swap current sense input for 50 V/V amplifier with 20 mV default sense limit, input current 150 μA maximum per pin at 20 V.
28 HS+ input Positive hot swap current sense input and supply input voltage measurement point, input current 150 μA maximum per pin at 20 V.
29 MO+ input Positive power monitor current sense input for 50 V/V amplifier with ±25 mV input range, input current 25 nA maximum at 20 V.
30 VCC power_in Positive supply input 4.5 to 20 V with quiescent current 5.5 mA; UVLO threshold 2.4 to 2.7 V rising with 90 to 120 mV hysteresis; GATE held low below UVLO.
31 UV input Undervoltage comparator input with 1.0 V reference threshold (0.99 to 1.01 V for A/AA grade), 45 to 75 mV hysteresis, input current 50 nA at voltages ≤3.6 V.
32 OV input Overvoltage comparator input with 1.0 V reference threshold (0.99 to 1.01 V for A/AA grade), 45 to 75 mV hysteresis, input current 50 nA at voltages ≤3.6 V.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-32(5x5)
Category Circuit Protection
Pins 33

CAD (KiCad official)

  • Symbol: ADM1278-1ACPZ-RL
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: adm1278-1acpz-rl-etched.step / adm1278-1acpz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adm1278-1acpz-rl.step / adm1278-1acpz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (61 pp, sha256 338e9e8a25e8f22f, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF