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ADM1066ACPZ

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Analog Devices Monitors & Reset Circuits, LFCSP-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADM1066ACPZ

Analog Devices · Monitors & Reset Circuits · LFCSP-40(6x6)

ADM1066ACPZ from Analog Devices, in a LFCSP-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VX1 input High-impedance input to a supply fault detector with thresholds from 0.573 V to 1.375 V, which can alternatively be used as a general-purpose digital input.
2 VX2 input High-impedance input to a supply fault detector with thresholds from 0.573 V to 1.375 V, which can alternatively be used as a general-purpose digital input.
3 VX3 input High-impedance input to a supply fault detector with thresholds from 0.573 V to 1.375 V, which can alternatively be used as a general-purpose digital input.
4 VX4 input High-impedance input to a supply fault detector with thresholds from 0.573 V to 1.375 V, which can alternatively be used as a general-purpose digital input.
5 VX5 input High-impedance input to a supply fault detector with thresholds from 0.573 V to 1.375 V, which can alternatively be used as a general-purpose digital input.
6 VP1 input Low-voltage supply fault detector input whose attenuator sets thresholds of 2.5 V to 6.0 V, 1.25 V to 3.00 V, or 0.573 V to 1.375 V.
7 VP2 input Low-voltage supply fault detector input whose attenuator sets thresholds of 2.5 V to 6.0 V, 1.25 V to 3.00 V, or 0.573 V to 1.375 V.
8 VP3 input Low-voltage supply fault detector input whose attenuator sets thresholds of 2.5 V to 6.0 V, 1.25 V to 3.00 V, or 0.573 V to 1.375 V.
9 VP4 input Low-voltage supply fault detector input whose attenuator sets thresholds of 2.5 V to 6.0 V, 1.25 V to 3.00 V, or 0.573 V to 1.375 V.
10 VH input High-voltage supply fault detector input whose attenuator sets thresholds of 6.0 V to 14.4 V or 2.5 V to 6.0 V.
11 AGND power_in Ground return for the input attenuators.
12 REFGND power_in Ground return for the on-chip reference circuits.
13 REFIN input ADC reference input, nominally 2.048 V, which must be driven by a reference voltage or connected to REFOUT.
14 REFOUT output On-chip 2.048 V reference output, typically connected to REFIN, with a 10 µF capacitor recommended between this pin and REFGND.
15 DAC1 output Voltage output DAC, high impedance at power-up, with output range 0.300 V to 1.551 V.
16 DAC2 output Voltage output DAC, high impedance at power-up, with output range 0.300 V to 1.551 V.
17 DAC3 output Voltage output DAC, high impedance at power-up, with output range 0.300 V to 1.551 V.
18 DAC4 output Voltage output DAC, high impedance at power-up, with output range 0.300 V to 1.551 V.
19 DAC5 output Voltage output DAC, high impedance at power-up, with output range 0.300 V to 1.551 V.
20 DAC6 output Voltage output DAC, high impedance at power-up, with output range 0.300 V to 1.551 V.
21 PDO10 output Programmable driver output, configurable as push/pull, open-collector with external pull-up, or open-collector with weak pull-up to VDDCAP or VPx.
22 PDO9 output Programmable driver output, configurable as push/pull, open-collector with external pull-up, or open-collector with weak pull-up to VDDCAP or VPx.
23 PDO8 output Programmable driver output, configurable as push/pull, open-collector with external pull-up, or open-collector with weak pull-up to VDDCAP or VPx.
24 PDO7 output Programmable driver output, configurable as push/pull, open-collector with external pull-up, or open-collector with weak pull-up to VDDCAP or VPx.
25 PDO6 output Programmable driver output with internally charge-pumped high drive for an external N-FET.
26 PDO5 output Programmable driver output with internally charge-pumped high drive for an external N-FET.
27 PDO4 output Programmable driver output with internally charge-pumped high drive for an external N-FET.
28 PDO3 output Programmable driver output with internally charge-pumped high drive for an external N-FET.
29 PDO2 output Programmable driver output with internally charge-pumped high drive for an external N-FET.
30 PDO1 output Programmable driver output with internally charge-pumped high drive for an external N-FET.
31 PDOGND power_in Ground return for the driver outputs.
32 VCCP power_out Central charge-pump voltage of 5.25 V, which requires a 10 µF reservoir capacitor to GND.
33 A0 input Logic input that sets the seventh bit of the SMBus interface address.
34 A1 input Logic input that sets the sixth bit of the SMBus interface address.
35 SCL bidirectional SMBus clock pin, an open-drain bidirectional pin that requires an external resistive pull-up.
36 SDA bidirectional SMBus data pin, an open-drain bidirectional pin that requires an external resistive pull-up.
37 AUX2 input Auxiliary single-ended ADC input.
38 AUX1 input Auxiliary single-ended ADC input.
39 VDDCAP power_out Device supply linearly regulated from the highest of VPx and VH to a typical 4.75 V, which requires a 10 µF capacitor to GND.
40 GND power_in Supply ground.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-40(6x6)
Category Power Supply Chip
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input High Voltage VIH 2 V Maximum VIN = 5.5 V 7
Input Low Voltage VIL 0.8 V Maximum VIN = 5.5 V 7
Input High Current IIH -1 µA VIN = 5.5 V 7
Input Low Current IIL 1 µA VIN = 0 V 7
Input Capacitance 5 pF 7
Programmable Pull-Down Current IPULL-DOWN 20 µA VDDCAP = 4.75 V, TA = 25°C, if known logic state is required 7
Input High Voltage (serial bus) VIH 2 V 7
Input Low Voltage (serial bus) VIL 0.8 V 7
Output Low Voltage VOL2 0.4 V IOUT = −3.0 mA 7
Clock Frequency fSCLK 400 kHz 7
Bus Free Time tBUF 1.3 µs 7
Start Setup Time tSU;STA 0.6 µs 7
Stop Setup Time tSU;STO 0.6 µs 7
Start Hold Time tHD;STA 0.6 µs 7
SCL Low Time tLOW 1.3 µs 7
SCL High Time tHIGH 0.6 µs 7
SCL, SDA Rise Time tR 300 ns 7
SCL, SDA Fall Time tF 300 ns 7
Data Setup Time tSU;DAT 100 ns 7
Data Hold Time tHD;DAT 5 ns 7
State Change Time 10 µs 7
Voltage on VH Pin 16 V 8
Voltage on VPx Pins 7 V 8
Voltage on VXx Pins -0.3 6.5 V 8
Voltage on AUX1, AUX2 Pins -0.3 5 V 8
Voltage on A0, A1 Pins -0.3 7 V 8
Voltage on REFIN, REFOUT Pins 5 V 8
Voltage on VDDCAP, VCCP Pins 6.5 V 8
Voltage on DACx Pins 6.5 V 8
Voltage on PDOx Pins 16 V 8
Voltage on SDA, SCL Pins 7 V 8
Voltage on GND, AGND, PDOGND, REFGND Pins -0.3 0.3 V 8
Input Current at Any Pin -5 5 mA 8
Package Input Current -20 20 mA 8
Maximum Junction Temperature TJ max 150 °C 8
Storage Temperature Range -65 150 °C 8
Lead Temperature, Soldering Vapor Phase 215 °C Vapor phase, 60 sec 8
ESD Rating, All Pins 2000 V All pins 8
Thermal Resistance, 40-Lead LFCSP θJA 25 °C/W Device soldered in circuit board, surface-mount package, worst-case 8

CAD (KiCad official)

  • Symbol: ADM1066ACPZ
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: LFCSP-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: adm1066acpz-etched.step / adm1066acpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adm1066acpz.step / adm1066acpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (36 pp, sha256 95bce4333939618b, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF