component

ADG758BCPZ-REEL7

Public Made by Adom

by adom

Analog Devices Signal Switches, Multiplexers, Decoders, LFCSP-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicadg758bcpz-reel7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

ADG758BCPZ-REEL7

Analog Devices · Signal Switches, Multiplexers, Decoders · LFCSP-20(4x4)

ADG758BCPZ-REEL7 from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable input that enables the device when high and switches all channels OFF when low.
2 VSS power_in Most negative supply in dual-supply operation; tied to ground at the device in single-supply applications.
3 S1 bidirectional Source terminal 1, may be an input or output.
4 S2 bidirectional Source terminal 2, may be an input or output.
5 S3 bidirectional Source terminal 3, may be an input or output.
6 S4 bidirectional Source terminal 4, may be an input or output.
7 D bidirectional Common drain terminal, may be an input or output.
8 NC unconnected No connect.
9 NC unconnected No connect.
10 S8 bidirectional Source terminal 8, may be an input or output.
11 S7 bidirectional Source terminal 7, may be an input or output.
12 S6 bidirectional Source terminal 6, may be an input or output.
13 S5 bidirectional Source terminal 5, may be an input or output.
14 VDD power_in Most positive power supply potential, 1.8 V to 5.5 V single supply.
15 GND power_in Ground (0 V) reference.
16 NC unconnected No connect.
17 A2 input Address bit 2 (MSB) of the 3-bit binary channel select input.
18 A1 input Address bit 1 of the 3-bit binary channel select input.
19 A0 input Address bit 0 (LSB) of the 3-bit binary channel select input.
20 NC unconnected No connect.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-20(4x4)
Category Logic
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
ON Resistance (RON) [VDD 5 V ±10%, single supply] RON 3 5 Ω VS = 0 V to VDD, IDS = 10 mA; Test Circuit 1 2
ON Resistance Match Between Channels (ΔRON) [VDD 5 V ±10%, single supply] ΔRON 0.4 0.8 Ω VS = 0 V to VDD, IDS = 10 mA 2
ON Resistance Flatness (RFLAT(ON)) [VDD 5 V ±10%, single supply] RFLAT(ON) 0.75 1.2 Ω VS = 0 V to VDD, IDS = 10 mA 2
Source OFF Leakage IS(OFF) [VDD = 5.5 V] IS(OFF) -0.3 0.01 0.3 nA VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 2 2
Drain OFF Leakage ID(OFF) [VDD = 5.5 V] ID(OFF) -0.75 0.01 0.75 nA VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 3 2
Channel ON Leakage ID, IS(ON) [VDD = 5.5 V] ID, IS (ON) -0.75 0.01 0.75 nA VD = VS = 1 V, or 4.5 V, Test Circuit 4 2
Input High Voltage VINH [VDD 5 V ±10%] VINH 2.4 V 2
Input Low Voltage VINL [VDD 5 V ±10%] VINL 0.8 V 2
Input Current IINL or IINH [VDD 5 V ±10%] IINL or IINH -0.1 0.005 0.1 µA VIN = VINL or VINH 2
Switching Time tTRANSITION [VDD 5 V ±10%] tTRANSITION 14 25 ns RL = 300 Ω, CL = 35 pF; Test Circuit 5 (typ); VS1 = 3 V/0 V, VS8 = 0 V/3 V (max) 2
Break-Before-Make Time Delay tD [VDD 5 V ±10%] tD 1 8 ns RL = 300 Ω, CL = 35 pF (typ); VS = 3 V; Test Circuit 6 (min) 2
Enable Delay tON(EN) [VDD 5 V ±10%] tON (EN) 14 25 ns RL = 300 Ω, CL = 35 pF (typ); VS = 3 V; Test Circuit 7 (max) 2
Enable Delay tOFF(EN) [VDD 5 V ±10%] tOFF (EN) 7 12 ns RL = 300 Ω, CL = 35 pF (typ); VS = 3 V; Test Circuit 7 (max) 2
Positive Supply Current IDD [VDD = 5.5 V] IDD 0.001 1 µA Digital Inputs = 0 V or 5.5 V 2
ON Resistance (RON) [VDD 3 V ±10%, single supply] RON 8 12 Ω VS = 0 V to VDD, IDS = 10 mA; Test Circuit 1 3
ON Resistance Match Between Channels (ΔRON) [VDD 3 V ±10%, single supply] ΔRON 0.4 1.2 Ω VS = 0 V to VDD, IDS = 10 mA 3
Source OFF Leakage IS(OFF) [VDD = 3.3 V] IS(OFF) -0.3 0.01 0.3 nA VS = 3 V/1 V, VD = 1 V/3 V; Test Circuit 2 3
Drain OFF Leakage ID(OFF) [VDD = 3.3 V] ID(OFF) -0.75 0.01 0.75 nA VS = 3 V/1 V, VD = 1 V/3 V; Test Circuit 3 3
Channel ON Leakage ID, IS(ON) [VDD = 3.3 V] ID, IS (ON) -0.75 0.01 0.75 nA VS = VD = 1 V or 3 V; Test Circuit 4 3
Input High Voltage VINH [VDD 3 V ±10%] VINH 2 V 3
Input Low Voltage VINL [VDD 3 V ±10%] VINL 0.8 V 3
Input Current IINL or IINH [VDD 3 V ±10%] IINL or IINH -0.1 0.005 0.1 µA VIN = VINL or VINH 3
Switching Time tTRANSITION [VDD 3 V ±10%] tTRANSITION 18 30 ns RL = 300 Ω, CL = 35 pF (typ); VS1 = 2 V/0 V, VS2 = 0 V/2 V (max) 3
Break-Before-Make Time Delay tD [VDD 3 V ±10%] tD 1 8 ns RL = 300 Ω, CL = 35 pF (typ); VS = 2 V; Test Circuit 6 (min) 3
Enable Delay tON(EN) [VDD 3 V ±10%] tON (EN) 18 30 ns RL = 300 Ω, CL = 35 pF (typ); VS = 2 V; Test Circuit 7 (max) 3
Enable Delay tOFF(EN) [VDD 3 V ±10%] tOFF (EN) 8 15 ns RL = 300 Ω, CL = 35 pF (typ); VS = 2 V; Test Circuit 7 (max) 3
Positive Supply Current IDD [VDD = 3.3 V] IDD 0.001 1 µA Digital Inputs = 0 V or 3.3 V 3
ON Resistance (RON) [dual supply VDD = +2.5 V, VSS = -2.5 V ±10%] RON 2.5 5 Ω VS = VSS to VDD, IDS = 10 mA; Test Circuit 1 4
ON Resistance Match Between Channels (ΔRON) [dual supply] ΔRON 0.4 0.8 Ω VS = VSS to VDD, IDS = 10 mA 4
ON Resistance Flatness (RFLAT(ON)) [dual supply] RFLAT(ON) 0.6 1 Ω VS = VSS to VDD, IDS = 10 mA 4
Source OFF Leakage IS(OFF) [VDD = +2.75 V, VSS = -2.75 V] IS(OFF) -0.3 0.01 0.3 nA VS = +2.25 V/-1.25 V, VD = -1.25 V/+2.25 V; Test Circuit 2 4
Drain OFF Leakage ID(OFF) [VDD = +2.75 V, VSS = -2.75 V] ID(OFF) -0.75 0.01 0.75 nA VS = +2.25 V/-1.25 V, VD = -1.25 V/+2.25 V; Test Circuit 3 4
Channel ON Leakage ID, IS(ON) [VDD = +2.75 V, VSS = -2.75 V] ID, IS (ON) -0.75 0.01 0.75 nA VS = VD = +2.25 V/-1.25 V; Test Circuit 4 4
Input High Voltage VINH [dual supply] VINH 1.7 V 4
Input Low Voltage VINL [dual supply] VINL 0.7 V 4
Input Current IINL or IINH [dual supply] IINL or IINH -0.1 0.005 0.1 µA VIN = VINL or VINH 4
Switching Time tTRANSITION [dual supply] tTRANSITION 14 25 ns RL = 300 Ω, CL = 35 pF (typ); VS = 1.5 V/0 V; Test Circuit 5 (max) 4
Break-Before-Make Time Delay tD [dual supply] tD 1 8 ns RL = 300 Ω, CL = 35 pF (typ); VS = 1.5 V; Test Circuit 6 (min) 4
Enable Delay tON(EN) [dual supply] tON (EN) 14 25 ns RL = 300 Ω, CL = 35 pF (typ); VS = 1.5 V; Test Circuit 7 (max) 4
Enable Delay tOFF(EN) [dual supply] tOFF (EN) 8 15 ns RL = 300 Ω, CL = 35 pF (typ); VS = 1.5 V; Test Circuit 7 (max) 4
Positive Supply Current IDD [VDD = +2.75 V] IDD 0.001 1 µA Digital Inputs = 0 V or 2.75 V 4
Negative Supply Current ISS [VSS = -2.75 V] ISS 0.001 1 µA VSS = -2.75 V; Digital Inputs = 0 V or 2.75 V 4
Thermal Impedance, Junction-to-Ambient (θJA), Chip Scale Package θJA 32 °C/W Chip Scale Package 5
VDD to VSS VDD to VSS 7 V 5
VDD to GND VDD to GND -0.3 7 V 5
VSS to GND VSS to GND -3.5 0.3 V 5
Analog Inputs (current limit) 30 mA VSS, 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 5
Digital Inputs (current limit) 30 mA -0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 5
Peak Current, S or D 100 mA Pulsed at 1 ms, 10% duty cycle max 5
Continuous Current, S or D 30 mA 5
Operating Temperature Range (Industrial, B Version) -40 85 °C 5
Storage Temperature Range -65 150 °C 5
Junction Temperature 150 °C 5
Lead Temperature, Soldering, Vapor Phase 215 °C Vapor phase (60 sec) 5
Lead Temperature, Soldering, Infrared 220 °C Infrared (15 sec) 5

CAD (KiCad official)

  • Symbol: ADG758BCPZ-REEL7
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)
  • 3D model files: adg758bcpz-reel7-etched.step / adg758bcpz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adg758bcpz-reel7.step / adg758bcpz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (12 pp, sha256 98b549de387dd5d1, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF