component

ADG714BRUZ-REEL7

Public Made by Adom

by adom

Analog Devices Analog Switches, Multiplexers, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfaceadg714bruz-reel7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 16d ago
viewers adg714bruz-reel7: viewers · Ray 16d ago
adg714bruz-reel7-etched.glb Publish 0.1.0 · Ray 16d ago
adg714bruz-reel7-etched.step adg714bruz-reel7: factory component page (tier=lcsc) · Ray 16d ago
adg714bruz-reel7-hero.glb adg714bruz-reel7: hero GLB from the etched model (keeps the MPN mark) · Ray 16d ago
adg714bruz-reel7-hero.overlay.json Publish 0.1.0 · Ray 16d ago
adg714bruz-reel7.glb Publish 0.1.0 · Ray 16d ago
adg714bruz-reel7.kicad_mod Publish 0.1.0 · Ray 16d ago
adg714bruz-reel7.kicad_sym Publish 0.1.0 · Ray 16d ago
adg714bruz-reel7.lbr Publish 0.1.0 · Ray 16d ago
adg714bruz-reel7.step Publish 0.1.0 · Ray 16d ago
package.json Publish 0.1.0 · Ray 16d ago
page.json Set visibility: public · Ray 16d ago
README.md Publish 0.1.0 · Ray 16d ago

ADG714BRUZ-REEL7

Analog Devices · Analog Switches, Multiplexers · TSSOP-24

ADG714BRUZ-REEL7 from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input Serial clock input; data is clocked into the input shift register on the falling edge, at serial input rates of up to 30 MHz.
2 VDD power_in Positive analog supply voltage.
3 DIN input Serial data input; data is clocked into the 8-bit input register on the falling edge of the serial clock.
4 GND power_in Ground reference.
5 S1 passive Source terminal of channel 1; may be an input or an output.
6 D1 passive Drain terminal of channel 1; may be an input or an output.
7 S2 passive Source terminal of channel 2; may be an input or an output.
8 D2 passive Drain terminal of channel 2; may be an input or an output.
9 S3 passive Source terminal of channel 3; may be an input or an output.
10 D3 passive Drain terminal of channel 3; may be an input or an output.
11 S4 passive Source terminal of channel 4; may be an input or an output.
12 D4 passive Drain terminal of channel 4; may be an input or an output.
13 D5 passive Drain terminal of channel 5; may be an input or an output.
14 S5 passive Source terminal of channel 5; may be an input or an output.
15 D6 passive Drain terminal of channel 6; may be an input or an output.
16 S6 passive Source terminal of channel 6; may be an input or an output.
17 D7 passive Drain terminal of channel 7; may be an input or an output.
18 S7 passive Source terminal of channel 7; may be an input or an output.
19 D8 passive Drain terminal of channel 8; may be an input or an output.
20 S8 passive Source terminal of channel 8; may be an input or an output.
21 VSS power_in Negative analog supply voltage; for single-supply operation, tie this pin to ground.
22 DOUT output Serial data output for daisy-chaining, clocked out on the rising edge of SCLK; open-drain output that must be pulled to the supply with an external pull-up resistor.
23 RESET input Active-low control input that clears the input register and turns all switches to the off condition.
24 SYNC input Active-low frame synchronization input; when taken high it updates the switches, and when low it powers on the SCLK and DIN buffers and enables the input shift register.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-24
Category Interface
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Single supply voltage (Features) VDD 2.7 5.5 V Single supply 1
VDD to VSS 7 V TA = 25°C 9
VDD to GND -0.3 7 V TA = 25°C 9
VSS to GND -3.5 0.3 V TA = 25°C 9
Peak current, Sx or Dx 100 mA Pulsed at 1 ms, 10% duty cycle maximum 9
Continuous current, Sx or Dx 30 mA 9
Operating temperature range -40 85 °C 9
Storage temperature range -65 150 °C 9
Junction temperature 150 °C 9
Lead temperature, soldering 300 °C 10 sec 9
Infrared reflow 235 °C 20 sec 9
Junction-to-ambient thermal resistance, RU-24 θJA 128 °C/W RU-24 package, JEDEC 2S2P board 9
Junction-to-case thermal resistance, RU-24 θJC 42 °C/W RU-24 package 9
SCLK cycle frequency fSCLK 30 MHz VDD = 2.7 V to 5.5 V; SCLK cycle frequency 7
SCLK cycle time t1 33 ns VDD = 2.7 V to 5.5 V 7
SCLK high time t2 13 ns VDD = 2.7 V to 5.5 V 7
SCLK low time t3 13 ns VDD = 2.7 V to 5.5 V 7
SYNC to SCLK rising edge setup time t4 0 ns VDD = 2.7 V to 5.5 V 7
Data setup time t5 5 ns VDD = 2.7 V to 5.5 V 7
Data hold time t6 4.5 ns VDD = 2.7 V to 5.5 V 7
SCLK falling edge to SYNC rising edge t7 0 ns VDD = 2.7 V to 5.5 V 7
Minimum SYNC high time t8 33 ns VDD = 2.7 V to 5.5 V 7
SCLK rising edge to DOUT valid t9 20 ns VDD = 2.7 V to 5.5 V; CL = 20 pF, RL = 1 kΩ 7
SCLK falling edge to SYNC falling edge t10 0 ns VDD = 2.7 V to 5.5 V 7
SYNC rising edge to SCLK rising edge t11 6 ns VDD = 2.7 V to 5.5 V 7
On Resistance RON 2.5 5 Ω −40°C to +85°C; VS = 0 V to VDD, IS = 10 mA; VDD = 5 V ± 10% 3
On Resistance Match Between Channels ΔRON 0.4 0.8 Ω VS = 0 V to VDD, IS = 10 mA; VDD = 5 V ± 10% 3
On Resistance Flatness RFLAT(ON) 0.6 1.2 Ω VS = 0 V to VDD, IS = 10 mA; VDD = 5 V ± 10% 3
Source Off Leakage IS(OFF) -0.3 0.01 0.3 nA −40°C to +85°C; VDD = 5.5 V; VD = 4.5 V/1 V, VS = 1 V/4.5 V 3
Drain Off Leakage ID(OFF) -0.3 0.01 0.3 nA −40°C to +85°C; VDD = 5.5 V; VD = 4.5 V/1 V, VS = 1 V/4.5 V 3
Channel On Leakage ID(ON), IS(ON) -0.3 0.01 0.3 nA −40°C to +85°C; VDD = 5.5 V; VD = VS = 1 V or 4.5 V 3
Input voltage high VINH 2.4 V VDD = 5 V ± 10% 3
Input voltage low VINL 0.8 V VDD = 5 V ± 10% 3
High or low input current IINH or IINL -0.1 0.005 0.1 µA VIN = VINL or VINH; VDD = 5 V ± 10% 3
Output voltage low, DOUT (ADG714) VOL 0.4 V ISINK = 6 mA 3
On Time (ADG714) tON 20 32 ns VS = 3 V, RL = 300 Ω, CL = 35 pF; VDD = 5 V ± 10% 3
Off Time (ADG714) tOFF 8 15 ns VS = 3 V, RL = 300 Ω, CL = 35 pF; VDD = 5 V ± 10% 4
Break-Before-Make Time Delay tD 1 8 ns VS = 3 V, RL = 300 Ω, CL = 35 pF; VDD = 5 V ± 10% 4
Positive Power Supply Current IDD 10 20 µA VDD = 5.5 V; digital inputs = 0 V or 5.5 V 4
On Resistance RON 6 12 Ω −40°C to +85°C; VS = 0 V to VDD, IS = 10 mA; VDD = 3 V ± 10% 4
On Resistance Match Between Channels ΔRON 0.4 1.2 Ω VS = 0 V to VDD, IS = 10 mA; VDD = 3 V ± 10% 4
Source OFF Leakage IS(OFF) -0.3 0.01 0.3 nA −40°C to +85°C; VDD = 3.3 V; VS = 3 V/1 V, VD = 1 V/3 V 4
Drain OFF Leakage ID(OFF) -0.3 0.01 0.3 nA −40°C to +85°C; VDD = 3.3 V; VS = 1 V/3 V, VD = 3 V/1 V 4
Channel ON Leakage ID(ON), IS(ON) -0.3 0.01 0.3 nA −40°C to +85°C; VDD = 3.3 V; VS = VD = 1 V or 3 V 4
Input voltage high VINH 2 V VDD = 3 V ± 10% 4
Input voltage low VINL 0.8 V VDD = 3 V ± 10% 4
Output voltage low, DOUT (ADG714) VOL 0.4 V ISINK = 6 mA; VDD = 3 V ± 10% 4
On Time (ADG714) tON 35 65 ns VS = 2 V, RL = 300 Ω, CL = 35 pF; VDD = 3 V ± 10% 5
Off Time (ADG714) tOFF 11 20 ns VS = 2 V, RL = 300 Ω, CL = 35 pF; VDD = 3 V ± 10% 5
Break-Before-Make Time Delay tD 1 8 ns VS = 2 V, RL = 300 Ω, CL = 35 pF; VDD = 3 V ± 10% 5
Positive Power Supply Current IDD 10 20 µA VDD = 3.3 V; digital inputs = 0 V or 3.3 V 5
On Resistance RON 2.5 5 Ω −40°C to +85°C; VS = VSS to VDD, IDS = 10 mA; VDD = +2.5 V ± 10%, VSS = −2.5 V ± 10% 5
On Resistance Flatness RFLAT(ON) 0.6 1 Ω VS = VSS to VDD, IDS = 10 mA; VDD = +2.5 V ± 10%, VSS = −2.5 V ± 10% 5
Source Off Leakage IS(OFF) -0.3 0.01 0.3 nA −40°C to +85°C; VDD = +2.75 V, VSS = −2.75 V; VS = +2.25 V/−1.25 V, VD = −1.25 V/+2.25 V 6
Drain Off Leakage ID(OFF) -0.3 0.01 0.3 nA −40°C to +85°C; VDD = +2.75 V, VSS = −2.75 V; VS = +2.25 V/−1.25 V, VD = −1.25 V/+2.25 V 6
Channel On Leakage ID(ON), IS(ON) -0.3 0.01 0.3 nA −40°C to +85°C; VDD = +2.75 V, VSS = −2.75 V; VS = VD = +2.25 V/−1.25 V 6
Input voltage high VINH 1.7 V VDD = +2.75 V, VSS = −2.75 V 6
Input voltage low VINL 0.7 V VDD = +2.75 V, VSS = −2.75 V 6
Positive Power Supply Current IDD 15 25 µA VDD = +2.75 V, VSS = −2.75 V; digital inputs = 0 V or VDD 7
Negative Power Supply Current ISS 15 25 µA VDD = +2.75 V, VSS = −2.75 V 7

CAD (KiCad official)

  • Symbol: ADG714BRUZ-REEL7
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: adg714bruz-reel7-etched.step / adg714bruz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adg714bruz-reel7.step / adg714bruz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (21 pp, sha256 315b2fb950e0fa91, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF