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ADG633YRUZ-REEL7

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Analog Devices Analog Switches, Multiplexers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADG633YRUZ-REEL7

Analog Devices · Analog Switches, Multiplexers · TSSOP-16

ADG633YRUZ-REEL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S2B passive Source terminal of multiplexer 2; can be an input or output.
2 S2A passive Source terminal of multiplexer 2; can be an input or output.
3 S3B passive Source terminal of multiplexer 3; can be an input or output.
4 D3 passive Drain terminal of multiplexer 3; can be an input or output.
5 S3A passive Source terminal of multiplexer 3; can be an input or output.
6 EN input Digital control input that disables all multiplexers when set high; the datasheet describes the digital inputs as TTL-/CMOS-compatible.
7 VSS power_in Most negative power supply terminal; tie to GND when the device is used with single-supply voltages.
8 GND power_in Ground (0 V) reference.
9 A2 input Digital control input that selects the switch states together with A1 and A0 per the truth table.
10 A1 input Digital control input that selects the switch states together with A2 and A0 per the truth table.
11 A0 input Digital control input that selects the switch states together with A2 and A1 per the truth table.
12 S1A passive Source terminal of multiplexer 1; can be an input or output.
13 S1B passive Source terminal of multiplexer 1; can be an input or output.
14 D1 passive Drain terminal of multiplexer 1; can be an input or output.
15 D2 passive Drain terminal of multiplexer 2; can be an input or output.
16 VDD power_in Most positive power supply terminal.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category Interface
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
On Resistance RON 52 100 Ω Dual ±5 V; TA −40°C to +125°C column; VS = ±4.5 V, IS = 1 mA; see Figure 20 3
On-Resistance Match Between Channels ΔRON 0.8 2 Ω Dual ±5 V; TA −40°C to +125°C column; VS = +3.5 V, IS = 1 mA 3
On-Resistance Flatness RFLAT(ON) 9 14 Ω Dual ±5 V; TA −40°C to +125°C column; VDD = +5 V, VSS = −5 V, VS = ±3 V, IS = 1 mA 3
Source Off Leakage IS(OFF) -5 0.005 5 nA Dual ±5 V; VDD = +5.5 V, VSS = −5.5 V; VD = ±4.5 V, VS = +4.5 V; see Figure 21 3
Drain Off Leakage ID(OFF) -5 0.005 5 nA Dual ±5 V; VDD = +5.5 V, VSS = −5.5 V; VD = ±4.5 V, VS = + 4.5 V; see Figure 22 3
Channel On Leakage ID(ON), IS(ON) -5 0.005 5 nA Dual ±5 V; VDD = +5.5 V, VSS = −5.5 V; VD = VS = ±4.5 V; see Figure 23 3
Input High Voltage VINH 2.4 V Dual ±5 V 3
Input Low Voltage VINL 0.8 V Dual ±5 V 3
Input Current IINL, IINH -1 0.005 1 μA Dual ±5 V; VIN = VINL or VINH 3
Transition Time tTRANSITION 60 130 ns Dual ±5 V; RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24 3
Enable Turn-On Time tON (EN) 70 135 ns Dual ±5 V; RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 3
Enable Turn-Off Time tOFF (EN) 25 50 ns Dual ±5 V; RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 3
Break-Before-Make Time Delay tBBM 10 40 ns Dual ±5 V; RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25 3
Charge Injection QINJ 2 4 pC Dual ±5 V; VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27 3
Positive Supply Current IDD 0.01 1 μA VDD = +5.5 V, VSS = −5.5 V; digital inputs = 0 V or 5.5 V 3
Negative Supply Current ISS 0.01 1 μA VDD = +5.5 V, VSS = −5.5 V; digital inputs = 0 V or 5.5 V 3
Analog Signal Range 0 V Single 5 V; VDD = 4.5 V, VSS = 0 V; TA −40°C to +125°C 4
On Resistance RON 85 200 Ω Single 5 V; VS = 0 V to 4.5 V, IS = 1 mA; see Figure 20 4
On-Resistance Match Between Channels ΔRON 4.5 10 Ω Single 5 V; VS = +3.5 V, IS = 1 mA 4
Source Off Leakage IS(OFF) -5 0.005 5 nA Single 5 V; VDD = 5.5 V; VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 21 4
Drain Off Leakage ID(OFF) -5 0.005 5 nA Single 5 V; VDD = 5.5 V; VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 22 4
Channel On Leakage ID(ON), IS(ON) -5 0.005 5 nA Single 5 V; VDD = 5.5 V; VS = VD = 1 V or 4.5 V; see Figure 23 4
Input High Voltage VINH 2.4 V Single 5 V 4
Input Low Voltage VINL 0.8 V Single 5 V 4
Input Current IINL, IINH -1 0.005 1 μA Single 5 V; VIN = VINL or VINH 4
Transition Time tTRANSITION 100 220 ns Single 5 V; RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24 4
Enable Turn-On Time tON (EN) 100 220 ns Single 5 V; RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 4
Enable Turn-Off Time tOFF (EN) 25 50 ns Single 5 V; RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26 4
Break-Before-Make Time Delay tBBM 10 90 ns Single 5 V; RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25 4
Charge Injection QINJ 0.5 1 pC Single 5 V; VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27 4
Positive Supply Current IDD 0.01 1 μA Single 5 V; VDD = 5.5 V; digital inputs = 0 V or 5.5 V 4
Analog Signal Range 0 V VDD = 2.7 V to 3.6 V, VSS = 0 V; VDD = 2.7 V; TA −40°C to +125°C 5
On Resistance RON 185 400 Ω VDD = 2.7 V to 3.6 V, VSS = 0 V; VS = 0 V to 2.7 V, IS = 0.1 mA; see Figure 20 5
On-Resistance Match Between Channels ΔRON 2 7 Ω VDD = 2.7 V to 3.6 V, VSS = 0 V; VS = +1.5 V, IS = 0.1 mA 5
Source Off Leakage IS(OFF) -5 0.005 5 nA VDD = 3.3 V; VS = 1 V/3 V, VD = 3 V/1 V; see Figure 21 5
Drain Off Leakage ID(OFF) -5 0.005 5 nA VDD = 3.3 V; VS = 1 V/3 V, VD = 3 V/1 V; see Figure 22 5
Channel On Leakage ID(ON), IS(ON) -5 0.005 5 nA VDD = 3.3 V; VS = VD = 1 V or 3 V; see Figure 23 5
Input High Voltage VINH 2 V VDD = 2.7 V to 3.6 V 5
Input Low Voltage VINL 0.5 V VDD = 2.7 V to 3.6 V 5
Input Current IINL, IINH -1 0.005 1 μA VDD = 2.7 V to 3.6 V; VIN = VINL or VINH 5
Transition Time tTRANSITION 170 400 ns VDD = 2.7 V to 3.6 V; RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 24 5
Enable Turn-On Time tON (EN) 200 420 ns VDD = 2.7 V to 3.6 V; RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26 5
Enable Turn-Off Time tOFF (EN) 30 75 ns VDD = 2.7 V to 3.6 V; RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26 5
Break-Before-Make Time Delay tBBM 10 180 ns VDD = 2.7 V to 3.6 V; RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 1.5 V; see Figure 25 5
Charge Injection QINJ 1 2 pC VDD = 2.7 V to 3.6 V; VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27 5
Positive Supply Current IDD 0.01 1 μA VDD = 3.3 V; digital inputs = 0 V or 3.3 V 5
VDD to VSS VDD − VSS 13 V 6
VDD to GND VDD − GND -0.3 13 V 6
VSS to GND VSS − GND -6.5 0.3 V Printed range +0.3 V to −6.5 V 6
Digital Inputs -0.3 V GND − 0.3 V to VDD + 0.3 V or 10 mA, whichever occurs first 6
Peak Current, S or D 40 mA Pulsed at 1 ms, 10% duty cycle maximum 6
Continuous Current, S or D 20 mA 6
Storage Temperature Range -65 150 °C 6
Junction Temperature 150 °C 6
Dual-Supply Operating Voltage (±) VDD, VSS 2 6 V ±2 V to ±6 V dual supply (magnitude) 1
Single-Supply Operating Voltage VDD 2 12 V 2 V to 12 V single supply 1
Low-Voltage Single-Supply Operating Voltage VDD 2.7 3.6 V VSS = 0 V; TA −40°C to +125°C 5
Operating Temperature Range TA -40 125 °C 6
Thermal Impedance, 16-Lead TSSOP θJA 150.4 °C/W 16-lead TSSOP (RU-16); single printed value, no min/max stated 6

CAD (KiCad official)

  • Symbol: ADG633YRUZ-REEL7
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: adg633yruz-reel7-etched.step / adg633yruz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adg633yruz-reel7.step / adg633yruz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (16 pp, sha256 32b37f78cb76dc28, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF