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ADG613YRUZ-REEL7
Public Made by Adomby adom
Analog Devices Analog Switches, Multiplexers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownADG613YRUZ-REEL7
Analog Devices · Analog Switches, Multiplexers · TSSOP-16
ADG613YRUZ-REEL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN1 | input | Switch 1 digital control input; per the ADG613 truth table, a logic 1 turns Switch 1 on and a logic 0 turns it off. |
| 2 | D1 | passive | Drain terminal of Switch 1, which can be an input or output. |
| 3 | S1 | passive | Source terminal of Switch 1, which can be an input or output. |
| 4 | VSS | power_in | Most negative power supply terminal; tie this pin to GND when the device is used with single-supply voltages. |
| 5 | GND | power_in | Ground (0 V) reference terminal. |
| 6 | S4 | passive | Source terminal of Switch 4, which can be an input or output. |
| 7 | D4 | passive | Drain terminal of Switch 4, which can be an input or output. |
| 8 | IN4 | input | Switch 4 digital control input; per the ADG613 truth table, a logic 1 turns Switch 4 on and a logic 0 turns it off. |
| 9 | IN3 | input | Switch 3 digital control input; per the ADG613 truth table, a logic 0 turns Switch 3 on and a logic 1 turns it off. |
| 10 | D3 | passive | Drain terminal of Switch 3, which can be an input or output. |
| 11 | S3 | passive | Source terminal of Switch 3, which can be an input or output. |
| 12 | NC | unconnected | Not internally connected. |
| 13 | VDD | power_in | Most positive power supply terminal. |
| 14 | S2 | passive | Source terminal of Switch 2, which can be an input or output. |
| 15 | D2 | passive | Drain terminal of Switch 2, which can be an input or output. |
| 16 | IN2 | input | Switch 2 digital control input; per the ADG613 truth table, a logic 0 turns Switch 2 on and a logic 1 turns it off. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| On Resistance, RON [dual supply ±5 V] | RON | 85 | 160 | Ω | VS = ±3 V, IS = −1 mA; see Figure 14 | 3 | |
| On-Resistance Match Between Channels, ΔRON [dual supply ±5 V] | ΔRON | 2 | 6.5 | Ω | VS = ±3 V, IS = −1 mA | 3 | |
| On-Resistance Flatness [dual supply ±5 V] | RFLAT(ON) | 25 | 60 | Ω | VS = ±3 V, IS = −1 mA | 3 | |
| Source Off Leakage [dual supply ±5 V] | IS(OFF) | -2 | 0.01 | 2 | nA | VD = ±4.5 V, VS = +4.5 V; see Figure 15 | 3 |
| Drain Off Leakage [dual supply ±5 V] | ID(OFF) | -2 | 0.01 | 2 | nA | VD = ±4.5 V, VS = + 4.5 V; see Figure 15 | 3 |
| Channel On Leakage [dual supply ±5 V] | ID(ON), IS(ON) | -6 | 0.01 | 6 | nA | VD = VS = ±4.5 V; see Figure 16 | 3 |
| Input High Voltage [dual supply ±5 V] | VINH | 2.4 | V | 3 | |||
| Input Low Voltage [dual supply ±5 V] | VINL | 0.8 | V | 3 | |||
| Input Current [dual supply ±5 V] | IINL or IINH | -0.1 | 0.005 | 0.1 | μA | VIN = VINL or VINH | 3 |
| Turn-On Time tON [dual supply ±5 V] | tON | 45 | 90 | ns | RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 | 3 | |
| Turn-Off Time tOFF [dual supply ±5 V] | tOFF | 25 | 50 | ns | RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 | 3 | |
| Break-Before-Make Time Delay [dual supply ±5 V] | tBBM | 10 | 15 | ns | RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 | 3 | |
| Positive Supply Current [dual supply ±5 V] | IDD | 0.001 | 1 | μA | Digital inputs = 0 V or 5.5 V | 3 | |
| Negative Supply Current [dual supply ±5 V] | ISS | 0.001 | 1 | μA | Digital inputs = 0 V or 5.5 V | 3 | |
| On Resistance, RON [single supply 5 V] | RON | 210 | 380 | Ω | VS = 3.5 V, IS = −1 mA; see Figure 14 | 4 | |
| On-Resistance Match Between Channels, ΔRON [single supply 5 V] | ΔRON | 3 | 13 | Ω | VS = 3.5 V, IS = −1 mA | 4 | |
| Source Off Leakage [single supply 5 V] | IS(OFF) | -2 | 0.01 | 2 | nA | VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15 | 4 |
| Drain Off Leakage [single supply 5 V] | ID(OFF) | -2 | 0.01 | 2 | nA | VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15 | 4 |
| Channel On Leakage [single supply 5 V] | ID(ON), IS(ON) | -6 | 0.01 | 6 | nA | VS = VD = 1 V or 4.5 V; see Figure 16 | 4 |
| Input High Voltage [single supply 5 V] | VINH | 2.4 | V | 4 | |||
| Input Low Voltage [single supply 5 V] | VINL | 0.8 | V | 4 | |||
| Input Current [single supply 5 V] | IINL or IINH | -0.1 | 0.005 | 0.1 | μA | VIN = VINL or VINH | 4 |
| Turn-On Time tON [single supply 5 V] | tON | 70 | 150 | ns | RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 | 4 | |
| Turn-Off Time tOFF [single supply 5 V] | tOFF | 25 | 50 | ns | RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 | 4 | |
| Break-Before-Make Time Delay [single supply 5 V] | tBBM | 10 | 25 | ns | RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 | 4 | |
| Positive Supply Current [single supply 5 V] | IDD | 0.001 | 1 | μA | Digital inputs = 0 V or 5.5 V | 4 | |
| On Resistance, RON [single supply 3 V] | RON | 380 | 460 | Ω | VS = 1.5 V, IS = −1 mA; see Figure 14 | 5 | |
| Source Off Leakage [single supply 3 V] | IS(OFF) | -2 | 0.01 | 2 | nA | VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15 | 5 |
| Drain Off Leakage [single supply 3 V] | ID(OFF) | -2 | 0.01 | 2 | nA | VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15 | 5 |
| Channel On Leakage [single supply 3 V] | ID(ON), IS(ON) | -6 | 0.01 | 6 | nA | VS = VD = 1 V or 3 V; see Figure 16 | 5 |
| Input High Voltage [single supply 3 V] | VINH | 2 | V | 5 | |||
| Input Low Voltage [single supply 3 V] | VINL | 0.8 | V | 5 | |||
| Input Current [single supply 3 V] | IINL or IINH | -0.1 | 0.005 | 0.1 | μA | VIN = VINL or VINH | 5 |
| Turn-On Time tON [single supply 3 V] | tON | 130 | 260 | ns | RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 | 5 | |
| Turn-Off Time tOFF [single supply 3 V] | tOFF | 40 | 65 | ns | RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 | 5 | |
| Break-Before-Make Time Delay [single supply 3 V] | tBBM | 10 | 50 | ns | RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18 | 5 | |
| Positive Supply Current [single supply 3 V] | IDD | 0.001 | 1 | μA | Digital inputs = 0 V or 3.3 V | 5 | |
| VDD to VSS | 13 | V | 6 | ||||
| VDD to GND | -0.3 | 6.5 | V | 6 | |||
| VSS to GND | -6.5 | 0.3 | V | 6 | |||
| Digital Inputs current limit | 30 | mA | Whichever occurs first, with GND − 0.3 V to VDD + 0.3 V | 6 | |||
| Peak Current, S or D | 20 | mA | Pulsed at 1 ms, 10% duty cycle maximum | 6 | |||
| Continuous Current, S or D | 10 | mA | 6 | ||||
| Continuous Current, S or D (3 V operation) | 7.5 | mA | 85°C to 125°C | 6 | |||
| Operating Temperature Range (Automotive, Y Version) | -40 | 125 | °C | 6 | |||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Junction Temperature | 150 | °C | 6 | ||||
| Lead Temperature, Soldering | 300 | °C | 10 sec | 6 | |||
| IR Reflow, Peak Temperature | 220 | °C | <20 sec | 6 | |||
| Reflow, Peak Temperature (Pb-Free) | 260 | °C | 6 | ||||
| Time at Peak Temperature (Pb-Free Reflow) | 20 | 40 | s | 6 | |||
| Thermal Impedance θJA, 16-Lead TSSOP | θJA | 150.4 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
ADG613YRUZ-REEL7 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
adg613yruz-reel7-etched.step/adg613yruz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adg613yruz-reel7.step/adg613yruz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (16 pp, sha256
5f8b562b88d1ae8c, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).