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ADG512BRZ-REEL7
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Analog Devices Analog Switches, Multiplexers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADG512BRZ-REEL7
Analog Devices · Analog Switches, Multiplexers · SOIC-16
ADG512BRZ-REEL7 from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN1 | input | Logic control input for switch 1 on the ADG512, where a logic high closes the switch; input thresholds are VINH 2.4 V min and VINL 0.8 V max. |
| 2 | D1 | passive | Drain terminal of switch 1, which may be an input or output, with analog signal range VDD to VSS in dual supply or 0 V to VDD in single supply. |
| 3 | S1 | passive | Source terminal of switch 1, which may be an input or output, with analog signal range VDD to VSS in dual supply or 0 V to VDD in single supply. |
| 4 | VSS | power_in | Most negative power supply potential (−4.5 V to −5.5 V in dual supply), which may be connected to GND in single supply applications. |
| 5 | GND | power_in | Ground (0 V) reference for the device. |
| 6 | S4 | passive | Source terminal of switch 4, which may be an input or output, with analog signal range VDD to VSS in dual supply or 0 V to VDD in single supply. |
| 7 | D4 | passive | Drain terminal of switch 4, which may be an input or output, with analog signal range VDD to VSS in dual supply or 0 V to VDD in single supply. |
| 8 | IN4 | input | Logic control input for switch 4 on the ADG512, where a logic high closes the switch; input thresholds are VINH 2.4 V min and VINL 0.8 V max. |
| 9 | IN3 | input | Logic control input for switch 3 on the ADG512, where a logic high closes the switch; input thresholds are VINH 2.4 V min and VINL 0.8 V max. |
| 10 | D3 | passive | Drain terminal of switch 3, which may be an input or output, with analog signal range VDD to VSS in dual supply or 0 V to VDD in single supply. |
| 11 | S3 | passive | Source terminal of switch 3, which may be an input or output, with analog signal range VDD to VSS in dual supply or 0 V to VDD in single supply. |
| 12 | NC | unconnected | No connect; this pin is not internally connected. |
| 13 | VDD | power_in | Most positive power supply potential, specified for 4.5 V to 5.5 V; absolute maximum VDD to GND is −0.3 V to +25 V. |
| 14 | S2 | passive | Source terminal of switch 2, which may be an input or output, with analog signal range VDD to VSS in dual supply or 0 V to VDD in single supply. |
| 15 | D2 | passive | Drain terminal of switch 2, which may be an input or output, with analog signal range VDD to VSS in dual supply or 0 V to VDD in single supply. |
| 16 | IN2 | input | Logic control input for switch 2 on the ADG512, where a logic high closes the switch; input thresholds are VINH 2.4 V min and VINL 0.8 V max. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| On Resistance RON (dual supply, B version, typ/max) | RON | 30 | 50 | Ω | VD = ±3.5 V, IS = -10 mA; VDD = +4.5 V, VSS = -4.5 V | 2 | |
| Source OFF Leakage IS(OFF) at 25°C (dual supply) | IS(OFF) | -0.1 | 0.025 | 0.1 | nA | VD = ±4.5 V, VS = 4.5 V; Test Circuit 2 | 2 |
| Source OFF Leakage IS(OFF) at -40°C to +85°C (dual supply) | IS(OFF) | -2.5 | 2.5 | nA | VD = ±4.5 V, VS = 4.5 V; Test Circuit 2 | 2 | |
| Drain OFF Leakage ID(OFF) at 25°C (dual supply) | ID(OFF) | -0.1 | 0.025 | 0.1 | nA | VD = ±4.5 V, VS = 4.5 V; Test Circuit 2 | 2 |
| Drain OFF Leakage ID(OFF) at -40°C to +85°C (dual supply) | ID(OFF) | -2.5 | 2.5 | nA | VD = ±4.5 V, VS = 4.5 V; Test Circuit 2 | 2 | |
| Channel ON Leakage ID, IS(ON) at 25°C (dual supply) | ID, IS (ON) | -0.2 | 0.05 | 0.2 | nA | VD = VS = ±4.5 V; Test Circuit 3 | 2 |
| Channel ON Leakage ID, IS(ON) at -40°C to +85°C (dual supply) | ID, IS (ON) | -5 | 5 | nA | VD = VS = ±4.5 V; Test Circuit 3 | 2 | |
| Input High Voltage (dual supply) | VINH | 2.4 | V | 2 | |||
| Input Low Voltage (dual supply) | VINL | 0.8 | V | 2 | |||
| Input Current IINL or IINH (dual supply) | IINL, IINH | -0.1 | 0.005 | 0.1 | µA | VIN = VINL or VINH | 2 |
| Turn-On Time tON (dual supply) | tON | 200 | 375 | ns | RL = 300 Ω, CL = 35 pF; VS = ±3 V; Test Circuit 4 | 2 | |
| Turn-Off Time tOFF (dual supply) | tOFF | 120 | 150 | ns | RL = 300 Ω, CL = 35 pF; VS = ±3 V; Test Circuit 4 | 2 | |
| Positive Supply Voltage VDD (dual supply) | VDD | 4.5 | 5.5 | V | VDD = +5 V ±10%, VSS = -5 V ±10% | 2 | |
| Negative Supply Voltage VSS (dual supply) | VSS | -4.5 | -5.5 | V | Printed as min/max -4.5/-5.5 V | 2 | |
| Supply Current IDD (dual supply) | IDD | 0.0001 | 11 | µA | typ: VDD = +5.5 V, VSS = -5.5 V; max: Digital Inputs = 0 V or 5 V | 2 | |
| Supply Current ISS (dual supply) | ISS | 0.0001 | 11 | µA | 2 | ||
| On Resistance RON (single supply, B version, typ/max) | RON | 45 | 75 | Ω | VD = 3.5 V, IS = -10 mA; VDD = 4.5 V | 3 | |
| Source OFF Leakage IS(OFF) at 25°C (single supply) | IS(OFF) | -0.1 | 0.025 | 0.1 | nA | VD = 4.5/1 V, VS = 14.5 V; Test Circuit 2 | 3 |
| Source OFF Leakage IS(OFF) at -40°C to +85°C (single supply) | IS(OFF) | -2.5 | 2.5 | nA | VD = 4.5/1 V, VS = 14.5 V; Test Circuit 2 | 3 | |
| Drain OFF Leakage ID(OFF) at 25°C (single supply) | ID(OFF) | -0.1 | 0.025 | 0.1 | nA | VD = 4.5/1 V, VS = 14.5 V; Test Circuit 2 | 3 |
| Drain OFF Leakage ID(OFF) at -40°C to +85°C (single supply) | ID(OFF) | -2.5 | 2.5 | nA | VD = 4.5/1 V, VS = 14.5 V; Test Circuit 2 | 3 | |
| Channel ON Leakage ID, IS(ON) at 25°C (single supply) | ID, IS (ON) | -0.2 | 0.05 | 0.2 | nA | VD = VS = 4.5 V/1 V; Test Circuit 3 | 3 |
| Channel ON Leakage ID, IS(ON) at -40°C to +85°C (single supply) | ID, IS (ON) | -5 | 5 | nA | VD = VS = 4.5 V/1 V; Test Circuit 3 | 3 | |
| Input High Voltage (single supply) | VINH | 2.4 | V | 3 | |||
| Input Low Voltage (single supply) | VINL | 0.8 | V | 3 | |||
| Input Current IINL or IINH (single supply) | IINL, IINH | -0.1 | 0.005 | 0.1 | µA | VIN = VINL or VINH | 3 |
| Turn-On Time tON (single supply) | tON | 250 | 500 | ns | RL = 300 Ω, CL = 35 pF; VS = 2 V; Test Circuit 4 | 3 | |
| Turn-Off Time tOFF (single supply) | tOFF | 50 | 100 | ns | RL = 300 Ω, CL = 35 pF; VS = 2 V; Test Circuit 4 | 3 | |
| Supply Voltage VDD (single supply) | VDD | 4.5 | 5.5 | V | VDD = 5 V ±10%, VSS = 0 V | 3 | |
| Supply Current IDD (single supply) | IDD | 0.0001 | 11 | µA | typ: VDD = 5.5 V; max: Digital Inputs = 0 V or 5 V | 3 | |
| Positive Supply to VSS (absolute maximum) | VDD to VSS | 44 | V | 5 | |||
| Positive Supply to GND (absolute maximum) | VDD to GND | -0.3 | 25 | V | 5 | ||
| Negative Supply to GND (absolute maximum) | VSS to GND | -25 | 0.3 | V | 5 | ||
| Analog, Digital Input Current (absolute maximum) | IIN | 30 | mA | or VSS, 2 V to VDD + 2 V, whichever occurs first | 5 | ||
| Continuous Current, S or D (absolute maximum) | IS, ID | 30 | mA | 5 | |||
| Peak Current, S or D (absolute maximum) | IS, ID peak | 100 | mA | Pulsed at 1 ms, 10% duty cycle max | 5 | ||
| Operating Temperature Range, Industrial (B Version) | TA | -40 | 85 | °C | B Version | 5 | |
| Storage Temperature Range | TSTG | -65 | 150 | °C | 5 | ||
| Junction Temperature | TJ | 150 | °C | 5 | |||
| SOIC Package Power Dissipation | PD | 600 | mW | SOIC package | 5 | ||
| θJA Thermal Impedance, SOIC | θJA | 77 | °C/W | SOIC package | 5 | ||
| Lead Temperature, Soldering Vapor Phase | TLEAD | 215 | °C | Vapor phase, 60 sec | 5 | ||
| Lead Temperature, Soldering Infrared | TLEAD | 220 | °C | Infrared, 15 sec | 5 |
CAD (KiCad official)
- Symbol:
ADG512BRZ-REEL7 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
adg512brz-reel7-etched.step/adg512brz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adg512brz-reel7.step/adg512brz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (12 pp, sha256
2561b10e7eb2c9fc, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).