ADG408BRZ-REEL

{
  "slug": "adg408brz-reel",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices Analog Switches, Multiplexers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "adg408brz-reel",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "adg408brz-reel.kicad_sym",
    "adg408brz-reel.kicad_mod",
    "adg408brz-reel.glb",
    "adg408brz-reel.step",
    "adg408brz-reel.lbr",
    "docs/hero.png",
    "docs/adg408brz-reel-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "adg408brz-reel-hero.glb",
    "adg408brz-reel-hero.overlay.json",
    "adg408brz-reel-etched.glb"
  ],
  "component": {
    "mpn": "ADG408BRZ-REEL",
    "manufacturer": "Analog Devices",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Interface",
    "subcategory": "Analog Switches, Multiplexers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884926724231169",
    "parts": {
      "symbol": "adg408brz-reel.kicad_sym",
      "footprint": "adg408brz-reel.kicad_mod",
      "model_3d": "adg408brz-reel-hero.glb",
      "model_3d_plain": "adg408brz-reel-etched.glb",
      "model_3d_step": "adg408brz-reel-etched.step",
      "model_3d_step_plain": "adg408brz-reel.step",
      "lbr": "adg408brz-reel.lbr"
    },
    "distributor_links": {
      "lcsc": "C496486",
      "digikey": "ADG408BRZ-REELTR-ND",
      "mouser": "584-ADG408BRZ-R"
    },
    "distributor_check": {
      "checked_at": "2026-10-13T02:40:10Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "ADG408BRZ-REELTR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "584-ADG408BRZ-R",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "A0",
        "type": "input",
        "description": "Logic control input (Ax) that selects the on-switch together with A1 and A2; VINH minimum is 2.4 V and VINL maximum is 0.8 V."
      },
      {
        "number": "2",
        "name": "EN",
        "type": "input",
        "description": "Active-high digital enable; when low the device is disabled and all switches are off, and when high the Ax inputs determine the on switch."
      },
      {
        "number": "3",
        "name": "VSS",
        "type": "power_in",
        "description": "Most negative power supply potential in dual supplies, which can be connected to ground in single-supply applications; VDD to VSS is rated 44 V maximum."
      },
      {
        "number": "4",
        "name": "S1",
        "type": "passive",
        "description": "Source terminal 1, which can be an input or an output, with analog signal range from VSS to VDD."
      },
      {
        "number": "5",
        "name": "S2",
        "type": "passive",
        "description": "Source terminal 2, which can be an input or an output, with analog signal range from VSS to VDD."
      },
      {
        "number": "6",
        "name": "S3",
        "type": "passive",
        "description": "Source terminal 3, which can be an input or an output, with analog signal range from VSS to VDD."
      },
      {
        "number": "7",
        "name": "S4",
        "type": "passive",
        "description": "Source terminal 4, which can be an input or an output, with analog signal range from VSS to VDD."
      },
      {
        "number": "8",
        "name": "D",
        "type": "passive",
        "description": "Common drain terminal, which can be an input or an output, with analog signal range from VSS to VDD."
      },
      {
        "number": "9",
        "name": "S8",
        "type": "passive",
        "description": "Source terminal 8, which can be an input or an output, with analog signal range from VSS to VDD."
      },
      {
        "number": "10",
        "name": "S7",
        "type": "passive",
        "description": "Source terminal 7, which can be an input or an output, with analog signal range from VSS to VDD."
      },
      {
        "number": "11",
        "name": "S6",
        "type": "passive",
        "description": "Source terminal 6, which can be an input or an output, with analog signal range from VSS to VDD."
      },
      {
        "number": "12",
        "name": "S5",
        "type": "passive",
        "description": "Source terminal 5, which can be an input or an output, with analog signal range from VSS to VDD."
      },
      {
        "number": "13",
        "name": "VDD",
        "type": "power_in",
        "description": "Most positive power supply potential; VDD to GND is rated −0.3 V to +32 V and VDD to VSS is rated 44 V maximum."
      },
      {
        "number": "14",
        "name": "GND",
        "type": "power_in",
        "description": "Ground (0 V) reference for the device."
      },
      {
        "number": "15",
        "name": "A2",
        "type": "input",
        "description": "Logic control input (Ax) that selects the on-switch together with A0 and A1; VINH minimum is 2.4 V and VINL maximum is 0.8 V."
      },
      {
        "number": "16",
        "name": "A1",
        "type": "input",
        "description": "Logic control input (Ax) that selects the on-switch together with A0 and A2; VINH minimum is 2.4 V and VINL maximum is 0.8 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet gives no separate pin figure or table for the SOIC-16 (R-16) package. The ADG408 pin n; The Figure 2 pin diagram text is garbled in the extracted datasheet, so the pin numbers were taken f; Pin types are KiCad-style classes assigned by me, not stated in the datasheet. S1–S8 and D are typed"
        ],
        "pages_sent": 15,
        "cost_usd": 0.0821,
        "at": "2026-10-13T02:39:53"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884926724231169",
        "pages": 15,
        "sha256": "5437cee29f2374b2",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "adg408brz-reel.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          9.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-13",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "adg408brz-reel-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "2023d704b53342cf7532ce9ed4ae17161aa26c220123e4d42e4226a5eb3149cf",
        "checked": "2026-10-13",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}