component

ADG1408YRUZ

Public Made by Adom

by adom

Analog Devices Analog Switches, Multiplexers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfaceadg1408yruzfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 15d ago
viewers adg1408yruz: viewers · Ray 15d ago
adg1408yruz-etched.glb Publish 0.1.0 · Ray 15d ago
adg1408yruz-etched.step adg1408yruz: factory component page (tier=lcsc) · Ray 15d ago
adg1408yruz-hero.glb adg1408yruz: hero GLB from the etched model (keeps the MPN mark) · Ray 15d ago
adg1408yruz-hero.overlay.json Publish 0.1.0 · Ray 15d ago
adg1408yruz.glb Publish 0.1.0 · Ray 15d ago
adg1408yruz.kicad_mod Publish 0.1.0 · Ray 15d ago
adg1408yruz.kicad_sym Publish 0.1.0 · Ray 15d ago
adg1408yruz.lbr Publish 0.1.0 · Ray 15d ago
adg1408yruz.step Publish 0.1.0 · Ray 15d ago
package.json Publish 0.1.0 · Ray 15d ago
page.json Set visibility: public · Ray 15d ago
README.md Publish 0.1.0 · Ray 15d ago

ADG1408YRUZ

Analog Devices · Analog Switches, Multiplexers · TSSOP-16

ADG1408YRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Logic control input for address bit A0; it is 3 V logic-compatible with VINH minimum 2.0 V and VINL maximum 0.8 V.
2 EN input Active high digital enable input; when low the device is disabled and all switches are off, and when high the Ax inputs determine which switch is on.
3 VSS power_in Most negative power supply potential; in single supply applications it can be connected to ground.
4 S1 passive Source terminal 1, which can be an input or an output.
5 S2 passive Source terminal 2, which can be an input or an output.
6 S3 passive Source terminal 3, which can be an input or an output.
7 S4 passive Source terminal 4, which can be an input or an output.
8 D passive Drain terminal, which can be an input or an output.
9 S8 passive Source terminal 8, which can be an input or an output.
10 S7 passive Source terminal 7, which can be an input or an output.
11 S6 passive Source terminal 6, which can be an input or an output.
12 S5 passive Source terminal 5, which can be an input or an output.
13 VDD power_in Most positive power supply potential; the datasheet rates VDD/VSS at ±4.5 V min to ±16.5 V max for dual supply.
14 GND power_in Ground (0 V) reference.
15 A2 input Logic control input for address bit A2; it is 3 V logic-compatible with VINH minimum 2.0 V and VINL maximum 0.8 V.
16 A1 input Logic control input for address bit A1; it is 3 V logic-compatible with VINH minimum 2.0 V and VINL maximum 0.8 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category Interface
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
On Resistance (RON) RON 6.7 Ω TA −40°C to +125°C; VDD = +13.5 V, VSS = −13.5 V 3
On Resistance Match Between Channels (ΔRON) ΔRON 1.1 Ω TA −40°C to +125°C; VS = ±10 V, IS = −10 mA 3
On-Resistance Flatness (RFLAT(ON)) RFLAT(ON) 0.92 Ω TA −40°C to +125°C; VS = ±10 V, IS = −10 mA 3
Source Off Leakage, IS (Off) IS (Off) -5 5 nA TA −40°C to +125°C; VDD = +16.5 V, VSS = −16.5 V; VS = ±10 V, VD = ∓10 V 3
Drain Off Leakage, ID (Off) ID (Off) -30 30 nA TA −40°C to +125°C; VDD = +16.5 V, VSS = −16.5 V; VS = ±10 V, VD = ∓10 V 3
Channel On Leakage, ID, IS (On) ID, IS (On) -30 30 nA TA −40°C to +125°C; VDD = +16.5 V, VSS = −16.5 V; VS = VD = ±10 V 3
Input High Voltage, VINH VINH 2 V 3
Input Low Voltage, VINL VINL 0.8 V 3
Input Current -0.1 0.1 μA VIN = VGND or VDD 3
Transition Time, tTRANSITION tTRANSITION 240 ns TA −40°C to +125°C; VS = 10 V; see Figure 29 3
Break-Before-Make Time Delay, tBBM tBBM 30 ns VS1 = VS2 = 10 V; see Figure 30 3
tON (EN) tON (EN) 165 ns TA −40°C to +125°C; VS = 10 V; see Figure 31 3
tOFF (EN) tOFF (EN) 170 ns TA −40°C to +125°C; VS = 10 V; see Figure 31 3
Positive supply current IDD IDD 1 μA TA −40°C to +125°C; VDD = +16.5 V, VSS = −16.5 V; digital inputs = 0 V or VDD 4
Positive supply current IDD IDD 380 μA TA −40°C to +125°C; VDD = +16.5 V, VSS = −16.5 V; digital inputs = 5 V 4
Negative supply current ISS ISS 1 μA TA −40°C to +125°C; VDD = +16.5 V, VSS = −16.5 V; digital inputs = 0 V, 5 V or VDD 4
Supply range VDD/VSS VDD/VSS 4.5 16.5 V 4
On Resistance (RON) RON 11.2 Ω TA −40°C to +125°C; VDD = 10.8 V, VSS = 0 V 5
On-Resistance Match Between Channels (ΔRON) ΔRON 1.1 Ω TA −40°C to +125°C; VS = 0 V to 10 V, IS = −10 mA 5
On-Resistance Flatness (RFLAT(ON)) RFLAT(ON) 2.8 Ω TA −40°C to +125°C; VS = 0 V to 10 V, IS = −10 mA 5
Source Off Leakage, IS (Off) IS (Off) -5 5 nA TA −40°C to +125°C; VDD = 13.2 V; VS = 1 V/10 V, VD = 10 V/1 V 5
Drain Off Leakage, ID (Off) ID (Off) -37 37 nA TA −40°C to +125°C; VDD = 13.2 V; VS = 1 V/10 V, VD = 10 V/1 V 5
Channel On Leakage, ID, IS (On) ID, IS (On) -32 32 nA TA −40°C to +125°C; VDD = 13.2 V; VS = VD = 1 V or 10 V 5
Input High Voltage, VINH VINH 2 V 5
Input Low Voltage, VINL VINL 0.8 V 5
Input Current -0.1 0.1 μA VIN = VGND or VDD 5
Transition Time, tTRANSITION tTRANSITION 380 ns TA −40°C to +125°C; VS = 8 V; see Figure 29 5
Break-Before-Make Time Delay, tBBM tBBM 40 ns VS1 = VS2 = 8 V; see Figure 30 5
tON (EN) tON (EN) 285 ns TA −40°C to +125°C; VS = 8 V; see Figure 31 5
tOFF (EN) tOFF (EN) 200 ns TA −40°C to +125°C; VS = 8 V; see Figure 31 5
Positive supply current IDD IDD 1 μA TA −40°C to +125°C; VDD = 13.2 V; digital inputs = 0 V or VDD 6
Positive supply current IDD IDD 380 μA TA −40°C to +125°C; VDD = 13.2 V; digital inputs = 5 V 6
Supply range VDD VDD 5 16.5 V VSS = 0 V, GND = 0 V 6
On Resistance (RON) RON 12 Ω TA −40°C to +125°C; VDD = +4.5 V, VSS = −4.5 V 7
On-Resistance Match Between Channels (ΔRON) ΔRON 1.1 Ω TA −40°C to +125°C; VS = ±4.5 V, IS = −10 mA 7
On-Resistance Flatness (RFLAT(ON)) RFLAT(ON) 3 Ω TA −40°C to +125°C; VS = ±4.5 V; IS = −10 mA 7
Source Off Leakage, IS (Off) IS (Off) -5 5 nA TA −40°C to +125°C; VDD = +5.5 V, VSS = −5.5 V; VS = ±4.5 V, VD = ∓4.5 V 7
Drain Off Leakage, ID (Off) ID (Off) -20 20 nA TA −40°C to +125°C; VDD = +5.5 V, VSS = −5.5 V; VS = ±4.5 V, VD = ∓4.5 V 7
Channel On Leakage, ID, IS (On) ID, IS (On) -22 22 nA TA −40°C to +125°C; VDD = +5.5 V, VSS = −5.5 V; VS = VD = ±4.5 V 7
Input High Voltage, VINH VINH 2 V 7
Input Low Voltage, VINL VINL 0.8 V 7
Input Current -0.1 0.1 μA VIN = VGND or VDD 7
Transition Time, tTRANSITION tTRANSITION 550 ns TA −40°C to +125°C; VS = 5 V; see Figure 29 7
Break-Before-Make Time Delay, tBBM tBBM 50 ns VS1 = VS2 = 5 V; see Figure 30 7
tON (EN) tON (EN) 440 ns TA −40°C to +125°C; VS = 5 V; see Figure 31 7
tOFF (EN) tOFF (EN) 370 ns TA −40°C to +125°C; VS = 5 V; see Figure 31 7
Positive supply current IDD IDD 1 μA TA −40°C to +125°C; VDD = +5.5 V, VSS = −5.5 V; digital inputs = 0 V or VDD 8
Negative supply current ISS ISS 1 μA TA −40°C to +125°C; VDD = +5.5 V, VSS = −5.5 V; digital inputs = 0 V, 5 V or VDD 8
Supply range VDD/VSS VDD/VSS 4.5 16.5 V 8
Continuous Current, S or D (15 V dual supply) 50 mA 125°C column; VDD = +13.5 V, VSS = −13.5 V 8
Continuous Current, S or D (12 V single supply) 50 mA 125°C column; VDD = 10.8 V, VSS = 0 V 8
Continuous Current, S or D (5 V dual supply) 45 mA 125°C column; VDD = +4.5 V, VSS = −4.5 V 8
VDD to VSS 35 V 9
VDD to GND -0.3 25 V 9
VSS to GND -25 0.3 V 9
Peak Current, S or D 350 mA pulsed at 1 ms, 10% duty cycle maximum 9
Operating Temperature Range, Industrial (Y Version) -40 125 °C 9
Storage Temperature Range -65 150 °C 9
Junction Temperature 150 °C 9
Thermal Resistance θJA, 16-Lead TSSOP θJA 150.4 °C/W device soldered in a circuit board (worst case) 9

CAD (KiCad official)

  • Symbol: ADG1408YRUZ
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: adg1408yruz-etched.step / adg1408yruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adg1408yruz.step / adg1408yruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (19 pp, sha256 8589fc50b566d2d5, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF