# ADF7021BCPZ-RL7

**Analog Devices** · RF Transceiver ICs · QFN-48-EP(7x7)

ADF7021BCPZ-RL7 from Analog Devices, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCOIN | passive | Regulator voltage for PA block and VCO cores; the tuning voltage on this pin sets the VCO output frequency, with higher tuning voltage giving higher output frequency. |
| 2 | CREG1 | power_out | Regulator voltage for PA block; a series 3.9 Ω resistor and a 100 nF capacitor between this pin and ground provide regulator stability and noise rejection. |
| 3 | VDD1 | power_in | Voltage supply for PA block and VCO cores; place 0.1 µF and 100 pF decoupling capacitors as close as possible to this pin and tie all VDD pins together. |
| 4 | RFOUT | output | Modulated signal output with output power from −16 dBm to +13 dBm; impedance match the output to the desired load. |
| 5 | RFGND | power_in | Ground for the transmitter output stage; tie all GND pins together. |
| 6 | RFIN | input | LNA input for the receiver section; input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. |
| 7 | RFINB | input | Complementary LNA input for the receiver section (see LNA/PA matching). |
| 8 | RLNA | passive | External bias resistor for the LNA; optimum value is 1.1 kΩ with 5% tolerance. |
| 9 | VDD4 | power_in | Voltage supply for LNA/mixer block; decouple to ground with a 10 nF capacitor. |
| 10 | RSET | passive | External resistor that sets charge pump current and some internal bias currents; use a 3.6 kΩ resistor with 5% tolerance. |
| 11 | CREG4 | power_out | Regulator voltage for LNA/mixer block; place a 100 nF capacitor between this pin and GND. |
| 12 | GND4 | power_in | Ground for LNA/mixer block. |
| 13 | MIX_I | unconnected | Signal chain test pin that is high impedance under normal conditions; leave unconnected. |
| 14 | MIX_I | unconnected | Complementary signal chain test pin that is high impedance under normal conditions; leave unconnected. |
| 15 | MIX_Q | unconnected | Signal chain test pin that is high impedance under normal conditions; leave unconnected. |
| 16 | MIX_Q | unconnected | Complementary signal chain test pin that is high impedance under normal conditions; leave unconnected. |
| 17 | FILT_I | unconnected | Signal chain test pin that is high impedance under normal conditions; leave unconnected. |
| 18 | FILT_I | unconnected | Complementary signal chain test pin that is high impedance under normal conditions; leave unconnected. |
| 19 | GND4 | power_in | Ground for LNA/mixer block. |
| 20 | FILT_Q | unconnected | Signal chain test pin that is high impedance under normal conditions; leave unconnected. |
| 21 | FILT_Q | unconnected | Complementary signal chain test pin that is high impedance under normal conditions; leave unconnected. |
| 22 | GND4 | power_in | Ground for LNA/mixer block. |
| 23 | TEST_A | unconnected | Signal chain test pin that is high impedance under normal conditions; leave unconnected. |
| 24 | CE | input | Chip enable; bringing CE low puts the device into complete power-down, register values are lost, and the device must be reprogrammed once CE is brought high. |
| 25 | SLE | input | Load enable CMOS input; when SLE goes high, data in the shift registers is loaded into one of four latches selected by the control bits. |
| 26 | SDATA | input | Serial data input, loaded MSB first with the 4 LSBs as control bits; high-impedance CMOS input. |
| 27 | SREAD | output | Serial data output that feeds readback data (for example AFC or ADC) to the microcontroller, clocked by SCLK. |
| 28 | SCLK | input | Serial clock input; data is latched into the 32-bit shift register on the rising clock edge; digital CMOS input. |
| 29 | GND2 | power_in | Ground for digital section. |
| 30 | ADCIN | input | Input to the internal 7-bit ADC; full scale is 0 V to 1.9 V and readback is made using the SREAD pin. |
| 31 | CREG2 | power_out | Regulator voltage for digital block; place a 100 nF capacitor between this pin and ground. |
| 32 | VDD2 | power_in | Voltage supply for digital block; place a 10 nF decoupling capacitor as close as possible to this pin. |
| 33 | SWD | output | Sync word detect output, asserted when the sync word sequence is matched, providing an interrupt to the external microcontroller. |
| 34 | TxRxDATA | bidirectional | Transmit data input and received data output with normal CMOS levels; in receive UART/SPI mode it outputs received data, and in transmit UART/SPI mode it is high impedance. |
| 35 | TxRxCLK | bidirectional | Data clock output in receive and transmit modes with normal CMOS levels; the positive edge is matched to the centre of the received data, and in UART/SPI transmit mode it is the transmit data input. |
| 36 | CLKOUT | output | Divided-down crystal reference clock output with 50:50 mark-space ratio, inverted relative to the reference; place a series 1 kΩ resistor as close as possible to the pin when used. |
| 37 | MUXOUT | output | Multiplexed output providing DIGITAL_LOCK_DETECT and other signals such as REGULATOR_READY to indicate PLL lock and serial interface regulator status. |
| 38 | OSC2 | passive | Connection for the reference crystal (between OSC1 and OSC2); a TCXO can drive this pin with CMOS levels when the internal crystal oscillator is disabled. |
| 39 | OSC1 | passive | Connection for the reference crystal (between OSC2 and OSC1); a TCXO can drive this pin with ac-coupled 0.8 V p-p levels when the internal crystal oscillator is enabled. |
| 40 | VDD3 | power_in | Voltage supply for charge pump and PLL dividers; decouple to ground with a 10 nF capacitor. |
| 41 | CREG3 | power_out | Regulator voltage for charge pump and PLL dividers; place a 100 nF capacitor between this pin and ground. |
| 42 | CPOUT | output | Charge pump output that generates current pulses integrated in the loop filter to change the VCO control voltage. |
| 43 | VDD | power_in | Voltage supply for XTAL and bandgap core; decouple to ground with a 10 nF capacitor. |
| 44 | L2 | passive | External VCO inductor pin; connect a chip inductor across L1 and L2 to set the VCO frequency, or leave floating when using the internal VCO inductor. |
| 45 | GND | power_in | Ground for VCO block. |
| 46 | L1 | passive | External VCO inductor pin; connect a chip inductor across L1 and L2 to set the VCO frequency, or leave floating when using the internal VCO inductor. |
| 47 | GND1 | power_in | Ground for VCO block. |
| 48 | CVCO | passive | Place a 22 nF capacitor between this pin and CREG1 to reduce VCO noise. |
| 49 | EPAD | power_in | Exposed pad that must be connected to GND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | QFN-48-EP(7x7) |
| Category | RF And Wireless |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Frequency range, direct output (external inductor VCO) |  | 160 |  | 650 | MHz | External inductor VCO | 5 |
| Frequency range, direct output (internal inductor VCO) |  | 862 |  | 950 | MHz | Internal inductor VCO | 5 |
| Frequency range, RF divide-by-2 (external inductor VCO) |  | 80 |  | 325 | MHz | External inductor VCO, RF divide-by-2 enabled | 5 |
| Frequency range, RF divide-by-2 (internal inductor VCO) |  | 431 |  | 475 | MHz | Internal inductor VCO, RF divide-by-2 enabled | 5 |
| Crystal reference frequency |  | 3.625 |  | 26 | MHz |  | 5 |
| External oscillator frequency |  | 3.625 |  | 30 | MHz |  | 5 |
| ADC integral nonlinearity (INL) | INL | -0.4 |  | 0.4 | LSB | VDD = 2.3 V to 3.6 V, TA = 25°C | 5 |
| ADC differential nonlinearity (DNL) | DNL | -0.4 |  | 0.4 | LSB | VDD = 2.3 V to 3.6 V, TA = 25°C | 5 |
| Data rate, 2FSK/3FSK |  | 0.05 |  | 251 | kbps | IF_BW = 25 kHz | 6 |
| Data rate, 4FSK |  | 0.05 |  | 32.82 | kbps | IF_BW = 25 kHz | 6 |
| Frequency deviation (fDEV) | fDEV | 0.056 |  | 28.26 | kHz | PFD = 3.625 MHz | 6 |
| Frequency deviation (fDEV) | fDEV | 0.306 |  | 156 | kHz | PFD = 20 MHz | 6 |
| Transmit power variation vs. temperature |  | -1 |  | 1 | dB | −40°C to +85°C | 6 |
| Transmit power variation vs. VDD |  | -1 |  | 1 | dB | 2.3 V to 3.6 V at 915 MHz, TA = 25°C | 6 |
| Transmit power flatness |  | -1 |  | 1 | dB | 902 MHz to 928 MHz, 3 V, TA = 25°C | 6 |
| Maximum transmit power |  |  |  | 13 | dBm | VDD = 3.0 V, TA = 25°C | 6 |
| Input current | IINH/IINL | -1 |  | 1 | µA |  | 10 |
| Output low voltage | VOL |  |  | 0.4 | V | IOL = 500 µA | 10 |
| Operating temperature range (TA) | TA | -40 |  | 85 | °C |  | 11 |
| Supply voltage | VDD | 2.3 |  | 3.6 | V | All VDD pins must be tied together | 11 |
| Power-down current, low power sleep mode |  |  | 0.1 | 1 | µA | CE low | 11 |
| Setup time, SDATA to SCLK | t1 | 10 |  |  | ns | SDATA to SCLK setup time | 11 |
| Hold time, SDATA to SCLK | t2 | 10 |  |  | ns | SDATA to SCLK hold time | 11 |
| SCLK high duration | t3 | 25 |  |  | ns | SCLK high duration | 11 |
| SCLK low duration | t4 | 25 |  |  | ns | SCLK low duration | 11 |
| Setup time, SCLK to SLE | t5 | 10 |  |  | ns | SCLK to SLE setup time | 11 |
| SLE pulse width | t6 | 20 |  |  | ns | SLE pulse width | 11 |
| SCLK to SREAD data valid, readback | t8 |  |  | 25 | ns | SCLK to SREAD data valid, readback | 11 |
| SREAD hold time after SCLK, readback | t9 |  |  | 25 | ns | SREAD hold time after SCLK, readback | 11 |
| SCLK to SLE disable time, readback | t10 | 10 |  |  | ns | SCLK to SLE disable time, readback | 11 |
| TxRxCLK negative edge to SLE | t11 | 5 |  |  | ns | 5 < t11 < (¼ × tBIT); upper limit is an expression, not numeric | 11 |
| TxRxDATA to TxRxCLK setup time (Tx mode) | t12 | 5 |  |  | ns | TxRxDATA to TxRxCLK setup time (Tx mode) | 11 |
| TxRxCLK to TxRxDATA hold time (Tx mode) | t13 | 5 |  |  | ns | TxRxCLK to TxRxDATA hold time (Tx mode) | 11 |
| VDD to GND | VDD | -0.3 |  | 5 | V |  | 15 |
| Analog I/O voltage to GND |  | -0.3 |  |  | V | Upper limit printed as AVDD + 0.3 V (expression, not numeric) | 15 |
| Digital I/O voltage to GND |  | -0.3 |  |  | V | Upper limit printed as DVDD + 0.3 V (expression, not numeric) | 15 |
| Operating temperature range, industrial (B version) |  | -40 |  | 85 | °C | Industrial (B Version) | 15 |
| Storage temperature range |  | -65 |  | 125 | °C |  | 15 |
| Maximum junction temperature |  |  |  | 150 | °C |  | 15 |
| Reflow soldering peak temperature |  |  |  | 260 | °C |  | 15 |
| Time at reflow peak temperature |  |  |  | 40 | sec |  | 15 |
| MLF thermal impedance, junction to ambient | θJA |  | 26 |  | °C/W | MLF package | 15 |

## CAD (KiCad official)

- Symbol: `ADF7021BCPZ-RL7`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `adf7021bcpz-rl7-etched.step` / `adf7021bcpz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adf7021bcpz-rl7.step` / `adf7021bcpz-rl7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885231335559168) (62 pp, sha256 `712a957a378855e6`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/adf7021bcpz-rl7-datasheet.pdf)