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ADF4360-7BCPZRL7
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Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+61@@ -0,0 +1,61 @@+# ADF4360-7BCPZRL7++**Analog Devices** · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-24(4x4)++ADF4360-7BCPZRL7 from Analog Devices, in a LFCSP-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CPGND | power_in | Charge pump ground return path. |+| 2 | AVDD | power_in | Analog power supply ranging from 3.0 V to 3.6 V with required decoupling capacitors. |+| 3 | AGND | power_in | Analog ground return path for prescaler and VCO. |+| 4 | RFOUTA | output | VCO output with programmable output level from −5 dBm to −14 dBm. |+| 5 | RFOUTB | output | VCO complementary output with programmable output level from −5 dBm to −14 dBm. |+| 6 | VVCO | power_in | Power supply for VCO ranging from 3.0 V to 3.6 V, must equal AVDD value with required decoupling. |+| 7 | VTUNE | input | Control input to VCO that determines output frequency via external filtering of charge pump output. |+| 8 | AGND | power_in | Analog ground return path for prescaler and VCO. |+| 9 | L1 | passive | External inductor to AGND setting output frequency, must match L2 with 470 Ω parallel resistor for values greater than 3.3 nH. |+| 10 | L2 | passive | External inductor to AGND setting output frequency, must match L1 with 470 Ω parallel resistor for values greater than 3.3 nH. |+| 11 | AGND | power_in | Analog ground return path for prescaler and VCO. |+| 12 | CC | passive | Internal VCO compensation node requiring 10 nF capacitor decoupling to ground. |+| 13 | RSET | passive | Charge pump output current setting resistor connected to CPGND with nominal voltage 0.6 V. |+| 14 | CN | passive | Internal VCO compensation node requiring 10 µF capacitor decoupling to VVCO. |+| 15 | DGND | power_in | Digital ground return path. |+| 16 | REFIN | input | Reference clock input, CMOS compatible with 100 kΩ input impedance, frequency 10 MHz to 250 MHz, can be ac-coupled. |+| 17 | CLK | input | Serial clock input latching data into 24-bit shift register on rising edge, high impedance CMOS input. |+| 18 | DATA | input | Serial data input loaded MSB first with two LSBs as control bits, high impedance CMOS input. |+| 19 | LE | input | Load enable CMOS input transferring shift register data to selected latch when driven high. |+| 20 | MUXOUT | output | Multiplexer output providing access to lock detect, scaled RF, or scaled reference frequency. |+| 21 | DVDD | power_in | Digital power supply ranging from 3.0 V to 3.6 V, must equal AVDD with required decoupling capacitors. |+| 22 | AGND | power_in | Analog ground return path for prescaler and VCO. |+| 23 | CE | input | Chip enable input, logic low powers down device and puts charge pump into three-state mode. |+| 24 | CP | output | Charge pump output providing ±ICP current to external loop filter driving internal VCO. |+| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LFCSP-24(4x4) |+| Category | Clock/Timing |+| Pins | 25 |++## CAD (KiCad official)++- Symbol: `ADF4360-7BCPZRL7`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`+- 3D model: LFCSP-24(4x4) (KiCad packages3D, STEP)+- 3D model files: `adf4360-7bcpzrl7-etched.step` / `adf4360-7bcpzrl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adf4360-7bcpzrl7.step` / `adf4360-7bcpzrl7.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588916610744111104) (25 pp, sha256 `a83566b064742e43`, retrieved 2026-09-18, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adf4360-7bcpzrl7-datasheet.pdf)
page.jsonadded+246@@ -0,0 +1,246 @@+{+ "slug": "adf4360-7bcpzrl7",+ "version": "0.1.0",+ "type": "component",+ "description": "Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-24(4x4). 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"model_3d_plain": "adf4360-7bcpzrl7.glb",+ "model_3d_step": "adf4360-7bcpzrl7-etched.step",+ "model_3d_step_plain": "adf4360-7bcpzrl7.step",+ "lbr": "adf4360-7bcpzrl7.lbr"+ },+ "distributor_links": {+ "lcsc": "C654698"+ },+ "pins": [+ {+ "number": "1",+ "name": "CPGND",+ "type": "power_in",+ "description": "Charge pump ground return path."+ },+ {+ "number": "2",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply ranging from 3.0 V to 3.6 V with required decoupling capacitors."+ },+ {+ "number": "3",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground return path for prescaler and VCO."+ },+ {+ "number": "4",+ "name": "RFOUTA",+ "type": "output",+ "description": "VCO output with programmable output level from −5 dBm to −14 dBm."+ },+ {+ "number": "5",+ "name": "RFOUTB",+ "type": "output",+ "description": "VCO complementary output with programmable output level from −5 dBm to −14 dBm."+ },+ {+ "number": "6",+ "name": "VVCO",+ "type": "power_in",+ "description": "Power supply for VCO ranging from 3.0 V to 3.6 V, must equal AVDD value with required decoupling."+ },+ {+ "number": "7",+ "name": "VTUNE",+ "type": "input",+ "description": "Control input to VCO that determines output frequency via external filtering of charge pump output."+ },+ {+ "number": "8",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground return path for prescaler and VCO."+ },+ {+ "number": "9",+ "name": "L1",+ "type": "passive",+ "description": "External inductor to AGND setting output frequency, must match L2 with 470 Ω parallel resistor for values greater than 3.3 nH."+ },+ {+ "number": "10",+ "name": "L2",+ "type": "passive",+ "description": "External inductor to AGND setting output frequency, must match L1 with 470 Ω parallel resistor for values greater than 3.3 nH."+ },+ {+ "number": "11",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground return path for prescaler and VCO."+ },+ {+ "number": "12",+ "name": "CC",+ "type": "passive",+ "description": "Internal VCO compensation node requiring 10 nF capacitor decoupling to ground."+ },+ {+ "number": "13",+ "name": "RSET",+ "type": "passive",+ "description": "Charge pump output current setting resistor connected to CPGND with nominal voltage 0.6 V."+ },+ {+ "number": "14",+ "name": "CN",+ "type": "passive",+ "description": "Internal VCO compensation node requiring 10 µF capacitor decoupling to VVCO."+ },+ {+ "number": "15",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground return path."+ },+ {+ "number": "16",+ "name": "REFIN",+ "type": "input",+ "description": "Reference clock input, CMOS compatible with 100 kΩ input impedance, frequency 10 MHz to 250 MHz, can be ac-coupled."+ },+ {+ "number": "17",+ "name": "CLK",+ "type": "input",+ "description": "Serial clock input latching data into 24-bit shift register on rising edge, high impedance CMOS input."+ },+ {+ "number": "18",+ "name": "DATA",+ "type": "input",+ "description": "Serial data input loaded MSB first with two LSBs as control bits, high impedance CMOS input."+ },+ {+ "number": "19",+ "name": "LE",+ "type": "input",+ "description": "Load enable CMOS input transferring shift register data to selected latch when driven high."+ },+ {+ "number": "20",+ "name": "MUXOUT",+ "type": "output",+ "description": "Multiplexer output providing access to lock detect, scaled RF, or scaled reference frequency."+ },+ {+ "number": "21",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital power supply ranging from 3.0 V to 3.6 V, must equal AVDD with required decoupling capacitors."+ },+ {+ "number": "22",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground return path for prescaler and VCO."+ },+ {+ "number": "23",+ "name": "CE",+ "type": "input",+ "description": "Chip enable input, logic low powers down device and puts charge pump into three-state mode."+ },+ {+ "number": "24",+ "name": "CP",+ "type": "output",+ "description": "Charge pump output providing ±ICP current to external loop filter driving internal VCO."+ },+ {+ "number": "25",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 25 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 25,+ "cost_usd": 0.3287,+ "at": "2026-09-18T05:51:27"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588916610744111104",+ "pages": 25,+ "sha256": "a83566b064742e43",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}