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ADF4360-7BCPZRL7

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Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-24(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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ADF4360-7BCPZRL7

Analog Devices · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-24(4x4)

ADF4360-7BCPZRL7 from Analog Devices, in a LFCSP-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CPGND power_in Charge pump ground return path.
2 AVDD power_in Analog power supply ranging from 3.0 V to 3.6 V with required decoupling capacitors.
3 AGND power_in Analog ground return path for prescaler and VCO.
4 RFOUTA output VCO output with programmable output level from −5 dBm to −14 dBm.
5 RFOUTB output VCO complementary output with programmable output level from −5 dBm to −14 dBm.
6 VVCO power_in Power supply for VCO ranging from 3.0 V to 3.6 V, must equal AVDD value with required decoupling.
7 VTUNE input Control input to VCO that determines output frequency via external filtering of charge pump output.
8 AGND power_in Analog ground return path for prescaler and VCO.
9 L1 passive External inductor to AGND setting output frequency, must match L2 with 470 Ω parallel resistor for values greater than 3.3 nH.
10 L2 passive External inductor to AGND setting output frequency, must match L1 with 470 Ω parallel resistor for values greater than 3.3 nH.
11 AGND power_in Analog ground return path for prescaler and VCO.
12 CC passive Internal VCO compensation node requiring 10 nF capacitor decoupling to ground.
13 RSET passive Charge pump output current setting resistor connected to CPGND with nominal voltage 0.6 V.
14 CN passive Internal VCO compensation node requiring 10 µF capacitor decoupling to VVCO.
15 DGND power_in Digital ground return path.
16 REFIN input Reference clock input, CMOS compatible with 100 kΩ input impedance, frequency 10 MHz to 250 MHz, can be ac-coupled.
17 CLK input Serial clock input latching data into 24-bit shift register on rising edge, high impedance CMOS input.
18 DATA input Serial data input loaded MSB first with two LSBs as control bits, high impedance CMOS input.
19 LE input Load enable CMOS input transferring shift register data to selected latch when driven high.
20 MUXOUT output Multiplexer output providing access to lock detect, scaled RF, or scaled reference frequency.
21 DVDD power_in Digital power supply ranging from 3.0 V to 3.6 V, must equal AVDD with required decoupling capacitors.
22 AGND power_in Analog ground return path for prescaler and VCO.
23 CE input Chip enable input, logic low powers down device and puts charge pump into three-state mode.
24 CP output Charge pump output providing ±ICP current to external loop filter driving internal VCO.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-24(4x4)
Category Clock/Timing
Pins 25

CAD (KiCad official)

  • Symbol: ADF4360-7BCPZRL7
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: LFCSP-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: adf4360-7bcpzrl7-etched.step / adf4360-7bcpzrl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adf4360-7bcpzrl7.step / adf4360-7bcpzrl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (25 pp, sha256 a83566b064742e43, retrieved 2026-09-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF