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ADF4351BCPZ-RL7

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Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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ADF4351BCPZ-RL7

Analog Devices · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-32(5x5)

ADF4351BCPZ-RL7 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK input Serial clock input; 32-bit data is loaded on CLK rising edges.
2 DATA input Serial data input; MSB-first with three LSBs serving as register select control bits.
3 LE input Load enable input; rising edge transfers data from shift register to selected internal register.
4 CE input Chip enable input; logic low disables device and tri-states charge pump, logic high enables operation.
5 SW input Fast lock switch input; must be connected to external loop filter when using fast lock mode.
6 VP power_in Charge pump power supply pin; voltage must equal AVDD (3.0 V to 3.6 V).
7 CPOUT output Charge pump output; sources and sinks current from 0.31 mA to 5.0 mA to external loop filter.
8 CPGND power_in Charge pump ground return; ground path for charge pump output.
9 AGND power_in Analog ground return path for AVDD.
10 AVDD power_in Analog power supply; operating range 3.0 V to 3.6 V, must equal DVDD, VVCO, SDVDD, and VP.
11 AGNDVCO power_in VCO analog ground return path.
12 RFOUTA+ output Positive RF output; output level programmable from -4 dBm to +5 dBm in 3 dB steps.
13 RFOUTA- output Negative RF output; complementary to RFOUTA+, output level programmable from -4 dBm to +5 dBm.
14 RFOUTB+ output Positive auxiliary RF output; output level programmable from -4 dBm to +5 dBm in 3 dB steps.
15 RFOUTB- output Negative auxiliary RF output; complementary to RFOUTB+, output level programmable from -4 dBm to +5 dBm.
16 VVCO power_in VCO power supply pin; voltage must equal AVDD (3.0 V to 3.6 V).
17 VVCO power_in VCO power supply pin; voltage must equal AVDD (3.0 V to 3.6 V).
18 AGNDVCO power_in VCO analog ground return path.
19 TEMP output Temperature compensation output; internal bias reference node requiring decoupling capacitor.
20 VTUNE input VCO tuning input; controls VCO output frequency with input range 0.5 V to 2.5 V.
21 AGNDVCO power_in VCO analog ground return path.
22 RSET input Charge pump current setting pin; connect external resistor to ground; sets ICP = 25.5/RSET (kΩ) from 0.31 mA to 5.0 mA with RSET from 10 kΩ to 3.9 kΩ.
23 VCOM output Internal compensation node; internal bias at half tuning range requiring decoupling capacitor.
24 VREF power_in Reference voltage output; internal bias reference requiring decoupling capacitor.
25 LD output Lock detect output; outputs logic high when PLL is locked, logic low when unlocked.
26 PDBRF input RF power down control input; logic low mutes RF outputs, also software programmable via register.
27 DGND power_in Digital ground return path for DVDD.
28 DVDD power_in Digital power supply; operating range 3.0 V to 3.6 V, must equal AVDD.
29 REFIN input Reference frequency input; CMOS input with nominal threshold AVDD/2; accepts 10 MHz to 250 MHz.
30 MUXOUT tri_state Multiplexer output; tri-state output for external monitoring of lock detect, N divider, or R divider selected by register bits.
31 SDGND power_in Sigma-delta modulator digital ground return path.
32 SDVDD power_in Sigma-delta modulator power supply; voltage must equal AVDD (3.0 V to 3.6 V).
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-32(5x5)
Category Clock/Timing
Pins 33

CAD (KiCad official)

  • Symbol: ADF4351BCPZ-RL7
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: adf4351bcpz-rl7-etched.step / adf4351bcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adf4351bcpz-rl7.step / adf4351bcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 bf842820730b1137, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF