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ADF4350BCPZ-RL7
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Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+69@@ -0,0 +1,69 @@+# ADF4350BCPZ-RL7++**Analog Devices** · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-32(5x5)++ADF4350BCPZ-RL7 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLK | input | Serial clock input; data is clocked into the 32-bit shift register on rising edges. |+| 2 | DATA | input | Serial data input; data is loaded MSB first with three LSBs as control bits. |+| 3 | LE | input | Load enable CMOS input; transfers data from shift register to selected register on rising edge. |+| 4 | CE | input | Chip enable; logic low powers down device and forces charge pump to three-state mode, logic high powers up device. |+| 5 | SW | input | Fast-lock switch; connection must be made from loop filter to this pin when using fast-lock mode. |+| 6 | VP | power_in | Charge pump power supply; must equal AVDD (3.0 V to 3.6 V) with decoupling capacitors placed close to this pin. |+| 7 | CPOUT | output | Charge pump output; provides ±ICP current to external loop filter when enabled. |+| 8 | CPGND | power_in | Charge pump ground; ground return path for CPOUT. |+| 9 | AGND | power_in | Analog ground; ground return pin for AVDD. |+| 10 | AVDD | power_in | Analog power supply; 3.0 V to 3.6 V with decoupling capacitors placed close to this pin. |+| 11 | AGNDVCO | power_in | VCO analog ground; ground return pin for the VCO. |+| 12 | RFOUTA+ | output | VCO output; programmable output level providing fundamental or divided VCO frequency (137.5 MHz to 4400 MHz). |+| 13 | RFOUTA− | output | Complementary VCO output; complementary to RFOUTA+ with programmable output level. |+| 14 | RFOUTB+ | output | Auxiliary VCO output; programmable output level providing fundamental or divided VCO frequency. |+| 15 | RFOUTB− | output | Complementary auxiliary VCO output; complementary to RFOUTB+ with programmable output level. |+| 16 | VVCO | power_in | VCO power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin. |+| 17 | VVCO | power_in | VCO power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin. |+| 18 | AGNDVCO | power_in | VCO analog ground; ground return pin for the VCO. |+| 19 | TEMP | output | Temperature compensation output; decoupling capacitors must be placed close to this pin. |+| 20 | VTUNE | input | VCO tuning voltage input; determines VCO output frequency in range 0.5 V to 2.5 V. |+| 21 | AGNDVCO | power_in | VCO analog ground; ground return pin for the VCO. |+| 22 | RSET | output | Charge pump current setting; connect resistor to GND to set charge pump output current (5.1 kΩ nominal sets 5 mA). |+| 23 | VCOM | output | Internal compensation node; biased at half the tuning range with decoupling capacitors placed close to this pin. |+| 24 | VREF | power_in | Reference voltage; internal reference node with decoupling capacitors placed close to this pin. |+| 25 | LD | output | Lock detect output pin; outputs logic high to indicate PLL lock and logic low for loss of lock. |+| 26 | PDBRF | input | RF power-down; logic low mutes RF outputs, also software controllable. |+| 27 | DGND | power_in | Digital ground; ground return path for DVDD. |+| 28 | DVDD | power_in | Digital power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin. |+| 29 | REFIN | input | Reference input; CMOS input with 100 kΩ input resistance and 10 MHz to 250 MHz frequency range. |+| 30 | MUXOUT | tri_state | Multiplexer output; three-state output providing access to lock detect, scaled RF, or scaled reference frequency. |+| 31 | SDGND | power_in | Digital sigma-delta modulator ground; ground return path for SDVDD. |+| 32 | SDVDD | power_in | Digital sigma-delta modulator power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin. |+| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LFCSP-32(5x5) |+| Category | Clock/Timing |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `ADF4350BCPZ-RL7`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)+- 3D model files: `adf4350bcpz-rl7-etched.step` / `adf4350bcpz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adf4350bcpz-rl7.step` / `adf4350bcpz-rl7.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884586361737217) (34 pp, sha256 `1b84903fa8212364`, retrieved 2026-09-21, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adf4350bcpz-rl7-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "adf4350bcpz-rl7",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "adf4350bcpz-rl7.kicad_sym",+ "adf4350bcpz-rl7.kicad_mod",+ "adf4350bcpz-rl7.glb",+ "adf4350bcpz-rl7.step",+ "adf4350bcpz-rl7.lbr",+ "docs/hero.png",+ "docs/adf4350bcpz-rl7-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ADF4350BCPZ-RL7",+ "manufacturer": "Analog Devices",+ "package": "LFCSP-32(5x5)",+ "pin_count": 33,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884586361737217",+ "parts": {+ "symbol": "adf4350bcpz-rl7.kicad_sym",+ "footprint": "adf4350bcpz-rl7.kicad_mod",+ "model_3d": "adf4350bcpz-rl7-etched.glb",+ "model_3d_plain": "adf4350bcpz-rl7.glb",+ "model_3d_step": "adf4350bcpz-rl7-etched.step",+ "model_3d_step_plain": "adf4350bcpz-rl7.step",+ "lbr": "adf4350bcpz-rl7.lbr"+ },+ "distributor_links": {+ "lcsc": "C98705"+ },+ "pins": [+ {+ "number": "1",+ "name": "CLK",+ "type": "input",+ "description": "Serial clock input; data is clocked into the 32-bit shift register on rising edges."+ },+ {+ "number": "2",+ "name": "DATA",+ "type": "input",+ "description": "Serial data input; data is loaded MSB first with three LSBs as control bits."+ },+ {+ "number": "3",+ "name": "LE",+ "type": "input",+ "description": "Load enable CMOS input; transfers data from shift register to selected register on rising edge."+ },+ {+ "number": "4",+ "name": "CE",+ "type": "input",+ "description": "Chip enable; logic low powers down device and forces charge pump to three-state mode, logic high powers up device."+ },+ {+ "number": "5",+ "name": "SW",+ "type": "input",+ "description": "Fast-lock switch; connection must be made from loop filter to this pin when using fast-lock mode."+ },+ {+ "number": "6",+ "name": "VP",+ "type": "power_in",+ "description": "Charge pump power supply; must equal AVDD (3.0 V to 3.6 V) with decoupling capacitors placed close to this pin."+ },+ {+ "number": "7",+ "name": "CPOUT",+ "type": "output",+ "description": "Charge pump output; provides ±ICP current to external loop filter when enabled."+ },+ {+ "number": "8",+ "name": "CPGND",+ "type": "power_in",+ "description": "Charge pump ground; ground return path for CPOUT."+ },+ {+ "number": "9",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground; ground return pin for AVDD."+ },+ {+ "number": "10",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; 3.0 V to 3.6 V with decoupling capacitors placed close to this pin."+ },+ {+ "number": "11",+ "name": "AGNDVCO",+ "type": "power_in",+ "description": "VCO analog ground; ground return pin for the VCO."+ },+ {+ "number": "12",+ "name": "RFOUTA+",+ "type": "output",+ "description": "VCO output; programmable output level providing fundamental or divided VCO frequency (137.5 MHz to 4400 MHz)."+ },+ {+ "number": "13",+ "name": "RFOUTA−",+ "type": "output",+ "description": "Complementary VCO output; complementary to RFOUTA+ with programmable output level."+ },+ {+ "number": "14",+ "name": "RFOUTB+",+ "type": "output",+ "description": "Auxiliary VCO output; programmable output level providing fundamental or divided VCO frequency."+ },+ {+ "number": "15",+ "name": "RFOUTB−",+ "type": "output",+ "description": "Complementary auxiliary VCO output; complementary to RFOUTB+ with programmable output level."+ },+ {+ "number": "16",+ "name": "VVCO",+ "type": "power_in",+ "description": "VCO power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin."+ },+ {+ "number": "17",+ "name": "VVCO",+ "type": "power_in",+ "description": "VCO power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin."+ },+ {+ "number": "18",+ "name": "AGNDVCO",+ "type": "power_in",+ "description": "VCO analog ground; ground return pin for the VCO."+ },+ {+ "number": "19",+ "name": "TEMP",+ "type": "output",+ "description": "Temperature compensation output; decoupling capacitors must be placed close to this pin."+ },+ {+ "number": "20",+ "name": "VTUNE",+ "type": "input",+ "description": "VCO tuning voltage input; determines VCO output frequency in range 0.5 V to 2.5 V."+ },+ {+ "number": "21",+ "name": "AGNDVCO",+ "type": "power_in",+ "description": "VCO analog ground; ground return pin for the VCO."+ },+ {+ "number": "22",+ "name": "RSET",+ "type": "output",+ "description": "Charge pump current setting; connect resistor to GND to set charge pump output current (5.1 kΩ nominal sets 5 mA)."+ },+ {+ "number": "23",+ "name": "VCOM",+ "type": "output",+ "description": "Internal compensation node; biased at half the tuning range with decoupling capacitors placed close to this pin."+ },+ {+ "number": "24",+ "name": "VREF",+ "type": "power_in",+ "description": "Reference voltage; internal reference node with decoupling capacitors placed close to this pin."+ },+ {+ "number": "25",+ "name": "LD",+ "type": "output",+ "description": "Lock detect output pin; outputs logic high to indicate PLL lock and logic low for loss of lock."+ },+ {+ "number": "26",+ "name": "PDBRF",+ "type": "input",+ "description": "RF power-down; logic low mutes RF outputs, also software controllable."+ },+ {+ "number": "27",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground; ground return path for DVDD."+ },+ {+ "number": "28",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin."+ },+ {+ "number": "29",+ "name": "REFIN",+ "type": "input",+ "description": "Reference input; CMOS input with 100 kΩ input resistance and 10 MHz to 250 MHz frequency range."+ },+ {+ "number": "30",+ "name": "MUXOUT",+ "type": "tri_state",+ "description": "Multiplexer output; three-state output providing access to lock detect, scaled RF, or scaled reference frequency."+ },+ {+ "number": "31",+ "name": "SDGND",+ "type": "power_in",+ "description": "Digital sigma-delta modulator ground; ground return path for SDVDD."+ },+ {+ "number": "32",+ "name": "SDVDD",+ "type": "power_in",+ "description": "Digital sigma-delta modulator power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 33 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 34,+ "cost_usd": 0.5899,+ "at": "2026-09-21T15:47:48"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884586361737217",+ "pages": 34,+ "sha256": "1b84903fa8212364",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}