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ADF4350BCPZ-RL7

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Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-32(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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ADF4350BCPZ-RL7

Analog Devices · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-32(5x5)

ADF4350BCPZ-RL7 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK input Serial clock input; data is clocked into the 32-bit shift register on rising edges.
2 DATA input Serial data input; data is loaded MSB first with three LSBs as control bits.
3 LE input Load enable CMOS input; transfers data from shift register to selected register on rising edge.
4 CE input Chip enable; logic low powers down device and forces charge pump to three-state mode, logic high powers up device.
5 SW input Fast-lock switch; connection must be made from loop filter to this pin when using fast-lock mode.
6 VP power_in Charge pump power supply; must equal AVDD (3.0 V to 3.6 V) with decoupling capacitors placed close to this pin.
7 CPOUT output Charge pump output; provides ±ICP current to external loop filter when enabled.
8 CPGND power_in Charge pump ground; ground return path for CPOUT.
9 AGND power_in Analog ground; ground return pin for AVDD.
10 AVDD power_in Analog power supply; 3.0 V to 3.6 V with decoupling capacitors placed close to this pin.
11 AGNDVCO power_in VCO analog ground; ground return pin for the VCO.
12 RFOUTA+ output VCO output; programmable output level providing fundamental or divided VCO frequency (137.5 MHz to 4400 MHz).
13 RFOUTA− output Complementary VCO output; complementary to RFOUTA+ with programmable output level.
14 RFOUTB+ output Auxiliary VCO output; programmable output level providing fundamental or divided VCO frequency.
15 RFOUTB− output Complementary auxiliary VCO output; complementary to RFOUTB+ with programmable output level.
16 VVCO power_in VCO power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin.
17 VVCO power_in VCO power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin.
18 AGNDVCO power_in VCO analog ground; ground return pin for the VCO.
19 TEMP output Temperature compensation output; decoupling capacitors must be placed close to this pin.
20 VTUNE input VCO tuning voltage input; determines VCO output frequency in range 0.5 V to 2.5 V.
21 AGNDVCO power_in VCO analog ground; ground return pin for the VCO.
22 RSET output Charge pump current setting; connect resistor to GND to set charge pump output current (5.1 kΩ nominal sets 5 mA).
23 VCOM output Internal compensation node; biased at half the tuning range with decoupling capacitors placed close to this pin.
24 VREF power_in Reference voltage; internal reference node with decoupling capacitors placed close to this pin.
25 LD output Lock detect output pin; outputs logic high to indicate PLL lock and logic low for loss of lock.
26 PDBRF input RF power-down; logic low mutes RF outputs, also software controllable.
27 DGND power_in Digital ground; ground return path for DVDD.
28 DVDD power_in Digital power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin.
29 REFIN input Reference input; CMOS input with 100 kΩ input resistance and 10 MHz to 250 MHz frequency range.
30 MUXOUT tri_state Multiplexer output; three-state output providing access to lock detect, scaled RF, or scaled reference frequency.
31 SDGND power_in Digital sigma-delta modulator ground; ground return path for SDVDD.
32 SDVDD power_in Digital sigma-delta modulator power supply; 3.0 V to 3.6 V equal to AVDD with decoupling capacitors placed close to this pin.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-32(5x5)
Category Clock/Timing
Pins 33

CAD (KiCad official)

  • Symbol: ADF4350BCPZ-RL7
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: adf4350bcpz-rl7-etched.step / adf4350bcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adf4350bcpz-rl7.step / adf4350bcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (34 pp, sha256 1b84903fa8212364, retrieved 2026-09-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF