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ADF4169CCPZ

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Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipadf4169ccpzfactory-2.0.0extractor-text

Verified ADF4169CCPZ

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 25 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADF4169CCPZ · LFCSP-24(4x4) · 25 pins
  • ✓copper: 25 copper pads, none touching another net
  • ✓datasheet: all 25 pin names found in the 36-page datasheet
  • ✓distributor: lcsc C578981, digikey 505-ADF4169CCPZ-ND, mouser 584-ADF4169CCPZ
  • ✓family: QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rnaf9flg/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.36)
  • ✓pads: 25 pins = 25 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 25 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ adf4169ccpz.kicad_sym✓ adf4169ccpz.kicad_mod✓ adf4169ccpz.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 3d ago
viewers adf4169ccpz: viewers · Ray 3d ago
adf4169ccpz-etched.glb Publish 0.1.0 · Ray 3d ago
adf4169ccpz-etched.step adf4169ccpz: factory component page (tier=mfr) · Ray 3d ago
adf4169ccpz-hero.glb adf4169ccpz: hero GLB from the etched model (keeps the MPN mark) · Ray 3d ago
adf4169ccpz-hero.overlay.json Publish 0.1.0 · Ray 3d ago
adf4169ccpz.glb Publish 0.1.0 · Ray 3d ago
adf4169ccpz.kicad_mod Publish 0.1.0 · Ray 3d ago
adf4169ccpz.kicad_sym Publish 0.1.0 · Ray 3d ago
adf4169ccpz.lbr Publish 0.1.0 · Ray 3d ago
adf4169ccpz.step Publish 0.1.0 · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Publish 0.1.0 · Ray 3d ago
verification.json Verified: Published by the parts factory: tier mfr, 25 pins · Ray 3d ago

ADF4169CCPZ

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-24(4x4)

ADF4169CCPZ from Analog Devices, in a LFCSP-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CPGND power_in Charge pump ground, the ground return path for the charge pump.
2 AGND power_in Analog ground; the exposed pad must be connected to AGND.
3 AGND power_in Analog ground; the exposed pad must be connected to AGND.
4 RFINB input Complementary RF prescaler input; decouple to the ground plane with a small bypass capacitor, typically 100 pF.
5 RFINA input RF prescaler input; a small-signal input normally ac-coupled from the VCO.
6 AVDD power_in Positive power supply for the RF section; decoupling capacitors should be placed as close as possible to the pin. Analog supply range is 2.7 V to 3.45 V.
7 AVDD power_in Positive power supply for the RF section; decoupling capacitors should be placed as close as possible to the pin. Analog supply range is 2.7 V to 3.45 V.
8 AVDD power_in Positive power supply for the RF section; decoupling capacitors should be placed as close as possible to the pin. Analog supply range is 2.7 V to 3.45 V.
9 REFIN input CMOS reference input with a nominal threshold of DVDD/2 and an equivalent input resistance of 100 kΩ; it can be driven from a TTL or CMOS crystal oscillator or ac-coupled.
10 DGND power_in Digital ground.
11 SDGND power_in Digital Σ-Δ modulator ground, the ground return path for the Σ-Δ modulator.
12 TXDATA input Transmit data pin that provides the transmitted data in FSK or PSK mode and also controls some ramping functionality.
13 CE input Chip enable (1.9 V logic); a logic low powers down the device and places the charge pump output into three-state mode.
14 CLK input Serial clock input used to clock serial data into the registers; data is latched into the input shift register on the CLK rising edge, and it is a high impedance CMOS input.
15 DATA input Serial data input loaded MSB first, with the three LSBs as control bits; it is a high impedance CMOS input.
16 LE input Load enable input; when LE is high, the data in the input shift register is loaded into one of the eight latches selected by the control bits, and it is a high impedance CMOS input.
17 MUXOUT output Multiplexer output that allows various internal signals to be accessed externally.
18 SDVDD power_in Power supply for the digital Σ-Δ modulator; decoupling capacitors should be placed as close as possible to the pin. Supply range is 1.8 V to 2 V.
19 DVDD power_in Positive power supply for the digital section; decoupling capacitors should be placed as close as possible to the pin. Supply range is 1.8 V to 2 V.
20 SW1 passive Fast lock switch.
21 SW2 passive Fast lock switch.
22 VP power_in Charge pump power supply; the voltage on this pin must be greater than or equal to AVDD. Supply range is 2.7 V to 3.45 V.
23 RSET passive A resistor between this pin and ground sets the maximum charge pump output current as ICP_MAX = 24.48/RSET; with RSET = 5.1 kΩ, ICP_MAX = 4.8 mA.
24 CP output Charge pump output that provides ±ICP to the external loop filter, which drives the external VCO.
25 EPAD power_in Exposed pad that must be connected to AGND.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-24(4x4)
Category RTC/Clock Chip
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
RF Input Frequency, RFIN RFIN 0.5 13.5 GHz −10 dBm minimum to 0 dBm maximum; for lower frequencies, ensure a slew rate ≥ 400 V/μs 3
Prescaler Output Frequency 2 GHz For higher frequencies, use 8/9 prescaler 3
REFIN Input Frequency 10 260 MHz −5 dBm minimum to +9 dBm maximum 3
Reference Doubler Enabled, REFIN frequency 10 50 MHz Bit DB20 in Register R2 set to 1 3
Phase Detector Frequency fPFD 130 MHz 3
ICP Sink/Source Current, High Value ICP 4.8 mA RSET = 5.1 kΩ 3
Absolute Accuracy (ICP) 2.5 % RSET = 5.1 kΩ 3
RSET Range RSET 4.59 5.1 5.61 kΩ 3
ICP Three-State Leakage Current 1 nA Sink and source current 3
Sink and Source Matching 2 % 0.5 V < VCP < VP − 0.5 V 3
ICP vs. VCP 2 % 0.5 V < VCP < VP − 0.5 V 3
ICP vs. Temperature 2 % VCP = VP/2 3
Input Voltage High VINH 1.17 V 3
Input Voltage Low VINL 0.4 V 3
Input Current IINH/IINL -1 1 μA 3
Input Capacitance CIN 10 pF 3
Output Voltage Low VOL 0.3 V IOL = 500 μA 3
Output High Current IOH 100 μA 3
Analog Supply Voltage AVDD 2.7 3.45 V 3
Digital Supply Voltage DVDD, SDVDD 1.8 2 V 3
Charge Pump Supply Voltage VP 2.7 3.45 V 3
AVDD Supply Current AIDD 26 40 mA Supply current drawn by AVDD; fPFD = 130 MHz 3
DVDD Supply Current DIDD 7.5 12 mA Supply current drawn by DVDD; fPFD = 130 MHz 3
VP Supply Current IP 5.5 7 mA Supply current drawn by VP; fPFD = 130 MHz 3
Power-Down Mode Current 2 μA 3
LE setup time t1 20 ns Write timing; limit at TMIN to TMAX 4
DATA to CLK setup time t2 10 ns Write timing; limit at TMIN to TMAX 4
DATA to CLK hold time t3 10 ns Write timing; limit at TMIN to TMAX 4
CLK high duration t4 25 ns Write timing; limit at TMIN to TMAX 4
CLK low duration t5 25 ns Write timing; limit at TMIN to TMAX 4
CLK to LE setup time t6 10 ns Write timing; limit at TMIN to TMAX 4
LE pulse width t7 20 ns Write timing; limit at TMIN to TMAX 4
TXDATA setup time t2 20 ns Read timing; CLK setup time to data (on MUXOUT) 5
CLK high duration (read) t3 25 ns Read timing 5
CLK low duration (read) t4 25 ns Read timing 5
CLK to LE setup time (read) t5 10 ns Read timing 5
Operating Temperature Range TA -40 125 °C Operating temperature (Table 1 footnote) 4
AVDD to GND AVDD -0.3 3.9 V 6
DVDD to GND DVDD -0.3 2.4 V 6
VP to GND VP -0.3 3.9 V 6
VP to AVDD VP-AVDD -0.3 0.3 V 6
Operating Temperature Range, Industrial -40 125 °C 6
Storage Temperature Range -65 125 °C 6
Maximum Junction Temperature 150 °C 6
Reflow Peak Temperature 260 °C Reflow soldering 6
Time at Peak Temperature 40 sec Reflow soldering 6
Charged Device Model (CDM) ESD 1000 V 6
Human Body Model (HBM) ESD 3000 V 6
Thermal Resistance, junction-to-ambient θJA 30.4 °C/W 24-Lead LFCSP_WQ; exposed pad soldered to AGND 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing Abs Human Body Model (HBM) 3000 V Stresses at or above those listed under Absolute Maximum 6

CAD (KiCad official)

  • Symbol: ADF4169CCPZ
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: LFCSP-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: adf4169ccpz-etched.step / adf4169ccpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adf4169ccpz.step / adf4169ccpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (36 pp, sha256 37ef570f5f14eaa4, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF