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ADF4002BCPZ

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Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-20(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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ADF4002BCPZ

Analog Devices · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-20(4x4)

ADF4002BCPZ from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CPGND power_in Charge pump ground return path.
2 AGND power_in Analog ground, RF input return path.
3 AGND power_in Analog ground, RF input return path (second connection).
4 RFINB input Complementary RF input, requires 100 pF bypass capacitor to ground.
5 RFINA input RF input, AC-coupled small signal from external VCO, 5 MHz to 400 MHz.
6 AVDD power_in Analog power supply, 2.7 V to 3.3 V, requires decoupling capacitors.
7 AVDD power_in Analog power supply, 2.7 V to 3.3 V, must equal DVDD (second connection).
8 REFIN input Reference input, CMOS level, 20 MHz to 300 MHz, VDD/2 threshold.
9 DGND power_in Digital ground return path.
10 DGND power_in Digital ground return path (second connection).
11 CE input Chip enable, logic low powers down device and tri-states charge pump.
12 CLK input Serial clock input for 24-bit shift register, maximum 20 MHz.
13 DATA input Serial data input, MSB first, controlled by control bits C2 and C1.
14 LE input Load enable, transfers shift register data to selected latch on rising edge.
15 MUXOUT tri_state Multiplexer output, selectable via M3-M1 for lock detect or frequency outputs, open-drain.
16 DVDD power_in Digital power supply, 2.7 V to 3.3 V, same as AVDD.
17 DVDD power_in Digital power supply, 2.7 V to 3.3 V, same as AVDD (second connection).
18 VP power_in Charge pump power supply, 2.7 V to 5.5 V, enables up to 5 V VCO tuning in 3 V systems.
19 RSET passive Connect external resistor (3.0 kΩ to 11 kΩ) between this pin and CPGND to set charge pump current.
20 CP tri_state Charge pump output, provides ±ICP to external loop filter, can be tri-stated via CE pin or control bits.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-20(4x4)
Category Clock/Timing
Pins 21

CAD (KiCad official)

  • Symbol: ADF4002BCPZ
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)
  • 3D model files: adf4002bcpz-etched.step / adf4002bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adf4002bcpz.step / adf4002bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (20 pp, sha256 fc5279ef463a7fa2, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF