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ADE7758ARWZRL

Public Made by Adom

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Analog Devices Energy Metering, SOIC-24-300mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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ADE7758ARWZRL

Analog Devices · Energy Metering · SOIC-24-300mil

ADE7758ARWZRL from Analog Devices, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 APCF output Active Power Calibration Frequency logic output providing active power information with full-scale output frequency scalable by writing to APCFNUM and APCFDEN registers.
2 DGND power_in Ground reference for digital circuitry (multiplier, filters, digital-to-frequency converter); acceptable to connect to analog ground plane.
3 DVDD power_in Digital Power Supply providing 5 V ± 5% for digital circuitry; decouple with 10 μF capacitor in parallel with 100 nF ceramic capacitor to DGND.
4 AVDD power_in Analog Power Supply providing 5 V ± 5% for analog circuitry; decouple with 10 μF capacitor in parallel with 100 nF ceramic capacitor to AGND.
5 IAP input Positive differential analog input for Phase A current channel with maximum differential input signal of ±0.5 V depending on PGA gain selection; overvoltage of ±6 V can be sustained without damage.
6 IAN input Negative differential analog input for Phase A current channel with maximum differential input signal of ±0.5 V depending on PGA gain selection; overvoltage of ±6 V can be sustained without damage.
7 IBP input Positive differential analog input for Phase B current channel with maximum differential input signal of ±0.5 V depending on PGA gain selection; overvoltage of ±6 V can be sustained without damage.
8 IBN input Negative differential analog input for Phase B current channel with maximum differential input signal of ±0.5 V depending on PGA gain selection; overvoltage of ±6 V can be sustained without damage.
9 ICP input Positive differential analog input for Phase C current channel with maximum differential input signal of ±0.5 V depending on PGA gain selection; overvoltage of ±6 V can be sustained without damage.
10 ICN input Negative differential analog input for Phase C current channel with maximum differential input signal of ±0.5 V depending on PGA gain selection; overvoltage of ±6 V can be sustained without damage.
11 AGND power_in Ground reference for analog circuitry (ADCs, temperature sensor, reference); tie to quiet analog ground plane with single connection point to digital ground plane.
12 REFIN/OUT bidirectional On-chip voltage reference (nominal 2.4 V ± 8%, 30 ppm/°C typical) or external reference input; decouple with 1 μF ceramic capacitor to AGND.
13 VN input Reference input for single-ended voltage channel with maximum signal level of ±0.5 V with respect to VN; overvoltage of ±6 V can be sustained without damage.
14 VCP input Single-ended analog input for Phase C voltage channel with maximum signal level of ±0.5 V with respect to VN; overvoltage of ±6 V can be sustained without damage.
15 VBP input Single-ended analog input for Phase B voltage channel with maximum signal level of ±0.5 V with respect to VN; overvoltage of ±6 V can be sustained without damage.
16 VAP input Single-ended analog input for Phase A voltage channel with maximum signal level of ±0.5 V with respect to VN; overvoltage of ±6 V can be sustained without damage.
17 VARCF output Reactive Power Calibration Frequency logic output providing reactive power or apparent power information (selected by VACF bit of WAVMODE register) with full-scale output frequency scalable via VARCFNUM and VARCFDEN registers.
18 IRQ output Active-low open-drain interrupt request output signaling active energy register half-level, apparent energy register half-level, or waveform sampling data available; requires external pull-up resistor.
19 CLKIN input Master clock input for ADCs and digital signal processing with specified frequency of 10 MHz (5-15 MHz range); accepts external clock or parallel resonant AT crystal.
20 CLKOUT output Crystal oscillator output pin; can drive one CMOS load when external clock is supplied at CLKIN or crystal is connected across CLKIN and CLKOUT.
21 CS input Active-low chip select logic input for 4-wire serial interface; allows ADE7758 to share serial bus with multiple devices.
22 DIN input Data input for synchronous serial interface; data is shifted in on the falling edge of SCLK.
23 SCLK input Serial clock input for synchronous serial interface with Schmitt-trigger input structure; all serial data transfers are synchronized to this clock.
24 DOUT tri_state Data output for synchronous serial interface; data is shifted out on the rising edge of SCLK and is normally in high impedance state unless driving data onto serial bus.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-24-300mil
Category Data Acquisition
Pins 24

CAD (KiCad official)

  • Symbol: ADE7758ARWZRL
  • Footprint: Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm
  • 3D model: SOIC-24-300mil (KiCad packages3D, STEP)
  • 3D model files: ade7758arwzrl-etched.step / ade7758arwzrl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ade7758arwzrl.step / ade7758arwzrl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (72 pp, sha256 e9056869364b2e8d, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF