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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADC3244IRGZT

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-48-EP(7x7)

ADC3244IRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground, 0 V reference pin.
2	DVDD	power_in	Digital 1.8-V power supply; recommended range 1.7 V to 1.9 V.
3	GND	power_in	Ground, 0 V reference pin.
4	DVDD	power_in	Digital 1.8-V power supply; recommended range 1.7 V to 1.9 V.
5	GND	power_in	Ground, 0 V reference pin.
6	AVDD	power_in	Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
7	AVDD	power_in	Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
8	AVDD	power_in	Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
9	AVDD	power_in	Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
10	INAP	input	Positive differential analog input for channel A; differential input up to 2 VPP for input frequencies below 450 MHz (1 VPP below 600 MHz), with input common-mode VCM ±0.025 V.
11	INAM	input	Negative differential analog input for channel A; differential input up to 2 VPP for input frequencies below 450 MHz (1 VPP below 600 MHz), with input common-mode VCM ±0.025 V.
12	AVDD	power_in	Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
13	SCLK	input	Serial interface clock input; has an internal 150-kΩ pull-down resistor.
14	SDATA	input	Serial interface data input; has an internal 150-kΩ pull-down resistor.
15	SEN	input	Serial interface enable, active low; has an internal 150-kΩ pull-up resistor to AVDD.
16	SDOUT	output	Serial interface data output.
17	AVDD	power_in	Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
18	CLKM	input	Negative differential clock input for the ADC; sampling clock 10 MSPS to 125 MSPS, amplitude 0.2 to 1.5 Vpp sine (ac-coupled).
19	CLKP	input	Positive differential clock input for the ADC; sampling clock 10 MSPS to 125 MSPS, amplitude 0.2 to 1.5 Vpp sine (ac-coupled).
20	AVDD	power_in	Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
21	RESET	input	Hardware reset, active high; has an internal 150-kΩ pull-down resistor.
22	SYSREFP	input	Positive external SYSREF input.
23	SYSREFM	input	Negative external SYSREF input.
24	VCM	output	Common-mode voltage output for the analog inputs.
25	AVDD	power_in	Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
26	INBM	input	Negative differential analog input for channel B; differential input up to 2 VPP for input frequencies below 450 MHz (1 VPP below 600 MHz), with input common-mode VCM ±0.025 V.
27	INBP	input	Positive differential analog input for channel B; differential input up to 2 VPP for input frequencies below 450 MHz (1 VPP below 600 MHz), with input common-mode VCM ±0.025 V.
28	AVDD	power_in	Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
29	AVDD	power_in	Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
30	AVDD	power_in	Analog 1.8-V power supply; recommended range 1.7 V to 1.9 V.
31	PDN	input	Power-down control, configurable via SPI; has an internal 150-kΩ pull-down resistor.
32	GND	power_in	Ground, 0 V reference pin.
33	DVDD	power_in	Digital 1.8-V power supply; recommended range 1.7 V to 1.9 V.
34	GND	power_in	Ground, 0 V reference pin.
35	DVDD	power_in	Digital 1.8-V power supply; recommended range 1.7 V to 1.9 V.
36	GND	power_in	Ground, 0 V reference pin.
37	DB1P	output	Positive serial LVDS output for channel B1.
38	DB1M	output	Negative serial LVDS output for channel B1.
39	DB0P	output	Positive serial LVDS output for channel B0.
40	DB0M	output	Negative serial LVDS output for channel B0.
41	FCLKP	output	Positive frame clock output.
42	FCLKM	output	Negative frame clock output.
43	DCLKP	output	Positive bit clock output.
44	DCLKM	output	Negative bit clock output.
45	DA1P	output	Positive serial LVDS output for channel A1.
46	DA1M	output	Negative serial LVDS output for channel A1.
47	DA0P	output	Positive serial LVDS output for channel A0.
48	DA0M	output	Negative serial LVDS output for channel A0.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-48-EP(7x7)
Category	Data Acquisition
Pins	49

CAD (KiCad official)

Symbol: ADC3244IRGZT
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: adc3244irgzt-etched.step / adc3244irgzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adc3244irgzt.step / adc3244irgzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (83 pp, sha256 1f2401e03508daeb, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF