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ADC122S706CIMTX
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Texas Instruments Analog To Digital Converters (ADC), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# ADC122S706CIMTX++**Texas Instruments** · Analog To Digital Converters (ADC) · TSSOP-14++ADC122S706CIMTX from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VREF | power_in | Voltage reference input that must be between 1V and VA, decoupled to GND with at least 0.1 µF ceramic (1.0 µF to 10 µF bulk in parallel recommended). |+| 2 | CHA+ | input | Non-inverting positive analog input for the differential signal on Channel A. |+| 3 | CHA− | input | Inverting negative analog input for the differential signal on Channel A. |+| 4 | GND | power_in | Ground reference point for all signals applied to the ADC122S706. |+| 5 | CHB- | input | Inverting negative analog input for the differential signal on Channel B. |+| 6 | CHB+ | input | Non-inverting positive analog input for the differential signal on Channel B. |+| 7 | VA | power_in | Analog supply input that must be between 4.5V and 5.5V, decoupled to GND with 0.1 µF ceramic in parallel with 1.0 µF to 10 µF bulk. |+| 8 | DUAL | input | Output mode select: logic high routes Channel A to DOUTA and Channel B to DOUTB; logic low routes both results to DOUTA (A first) with DOUTB high impedance. |+| 9 | GND | power_in | Ground reference point for all signals applied to the ADC122S706. |+| 10 | VD | power_in | Digital supply input that must be between 2.7V and VA, decoupled to GND with 0.1 µF ceramic in parallel with 1.0 µF to 10 µF bulk. |+| 11 | DOUTA | output | Serial data output for Channel A, 4 null bits then 12 data bits MSB first, clocked out on SCLK falling edges and generally valid on rising edges. |+| 12 | DOUTB | output | Serial data output for Channel B, 4 null bits then 12 data bits MSB first, clocked out on SCLK falling edges; high impedance when DUAL is logic low. |+| 13 | SCLK | input | Serial clock that controls data transfer and serves as the conversion clock, operated within 8 MHz to 16 MHz. |+| 14 | CS | input | Active-low chip select: Normal Mode when LOW and Power-Down Mode when HIGH, with a conversion beginning on the falling edge of CS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Data Acquisition |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `ADC122S706CIMTX`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `adc122s706cimtx-etched.step` / `adc122s706cimtx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc122s706cimtx.step` / `adc122s706cimtx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc122s706) (34 pp, sha256 `a9196ee2d5d59e90`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adc122s706cimtx-datasheet.pdf)
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logic low routes both results to DOUTA (A first) with DOUTB high impedance."+ },+ {+ "number": "9",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference point for all signals applied to the ADC122S706."+ },+ {+ "number": "10",+ "name": "VD",+ "type": "power_in",+ "description": "Digital supply input that must be between 2.7V and VA, decoupled to GND with 0.1 µF ceramic in parallel with 1.0 µF to 10 µF bulk."+ },+ {+ "number": "11",+ "name": "DOUTA",+ "type": "output",+ "description": "Serial data output for Channel A, 4 null bits then 12 data bits MSB first, clocked out on SCLK falling edges and generally valid on rising edges."+ },+ {+ "number": "12",+ "name": "DOUTB",+ "type": "output",+ "description": "Serial data output for Channel B, 4 null bits then 12 data bits MSB first, clocked out on SCLK falling edges; high impedance when DUAL is logic low."+ },+ {+ "number": "13",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock that controls data transfer and serves as the conversion clock, operated within 8 MHz to 16 MHz."+ },+ {+ "number": "14",+ "name": "CS",+ "type": "input",+ "description": "Active-low chip select: Normal Mode when LOW and Power-Down Mode when HIGH, with a conversion beginning on the falling edge of CS."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The connection diagram text on page 2 is garbled in extraction, so the pin-to-name mapping was taken; The 8 MHz to 16 MHz clock range in the SCLK description comes from the Operating Ratings on page 4, "+ ],+ "pages_sent": 7,+ "cost_usd": 0.0507,+ "at": "2026-10-08T19:29:17"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/adc122s706",+ "pages": 34,+ "sha256": "a9196ee2d5d59e90",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "adc122s706cimtx.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "adc122s706cimtx-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "0f9ecf25a04d0720d7c0bded52799ee3d5736edfd5f67aab73670017604e03d8",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}