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ADC121S625CIMMX

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Texas Instruments Analog To Digital Converters (ADCs), VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADC121S625CIMMX

Texas Instruments · Analog To Digital Converters (ADCs) · VSSOP-8-0.65mm

ADC121S625CIMMX from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_in Reference voltage input; the reference can be varied from 100mV to 2.5V, with best performance between 500mV and 2.5V.
2 +IN input Non-inverting differential analog input, with the differential input range limited to -VREF to +VREF.
3 -IN input Inverting differential analog input, with the differential input range limited to -VREF to +VREF.
4 GND power_in Ground pin, the reference for all voltages on the device.
5 CS input Chip select: the ADC is active when LOW and enters power-down when HIGH, and a conversion begins on the falling edge of CS.
6 DOUT output Serial data output of 12 bits, valid on the falling edge of SCLK, with the serial output enabled by the second SCLK pulse after CS falls.
7 SCLK input Serial clock that controls data transfer and also serves as the conversion clock, with a clock range of 0.8 MHz to 3.2 MHz.
8 VA power_in Analog power supply input, operating from 4.5V to 5.5V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSSOP-8-0.65mm
Category Data Converters
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog Supply Voltage VA -0.3 6.5 V 3
Voltage on Any Pin to GND -0.3 V Maximum printed as VA + 0.3V 3
Input Current at Any Pin -10 10 mA 3
Package Input Current -50 50 mA 3
ESD Susceptibility Human Body Model 2500 V Human body model 3
ESD Susceptibility Machine Model 250 V Machine model 3
ESD Susceptibility Charge Device Model 750 V Charge device model 3
Soldering Temperature 260 °C Infrared, 10 seconds 3
Junction Temperature 150 °C 3
Storage Temperature -65 150 °C 3
Operating Temperature Range TA -40 85 °C 3
Supply Voltage VA 4.5 5.5 V 3
Reference Voltage VREF 0.1 2.5 V 3
Digital Input Pins Voltage Range 0 V Maximum printed as VA 3
Clock Frequency fSCLK 0.8 3.2 MHz 3
Integral Non-Linearity INL -1 1 LSB 4
Differential Non-Linearity DNL -0.75 0.4 0.75 LSB 4
Offset Error OE -4 0.4 4 LSB 4
Gain Error GE -4 -0.05 4 LSB 4
Signal-to-Noise Plus Distortion Ratio SINAD 68.5 72.6 dBc fIN = 20 kHz, -0.1 dBFS 4
Signal-to-Noise Ratio SNR 70 72.9 dBc fIN = 20 kHz, -0.1 dBFS 4
Total Harmonic Distortion THD -84 -74 dBc fIN = 20 kHz, -0.1 dBFS 4
Spurious-Free Dynamic Range SFDR 74 85.2 dBc fIN = 20 kHz, -0.1 dBFS 4
Effective Number of Bits ENOB 11.1 11.8 bits fIN = 20 kHz, -0.1 dBFS 4
DC Leakage Current IDCL -2 0.04 2 µA 4
Reference Voltage Range VREF 0.1 2.5 V 4
Input High Voltage VIH 2.4 V VA = 4.5V to 5.5V 4
Input Low Voltage VIL 0.8 V VA = 4.5V to 5.5V 4
Input Current IIN -1 0.03 1 µA VIN = 0V or VA 4
Input Capacitance CIND 2 4 pF 4
Output Low Voltage VOL 0.02 0.4 V VA = 4.5V to 5.5V, ISINK = 250 µA 5
TRI-STATE Leakage Current IOZH, IOZL -1 0.03 1 µA 5
TRI-STATE Output Capacitance COUT 2 4 pF 5
Analog Supply Voltage VA 4.5 5.5 V 5
Supply Current, Normal Mode Active IA 410 510 µA fSCLK = 3.2 MHz, fSMPL = 200 ksps, fIN = 20 kHz, CL = 15pF 5
Shutdown Supply Current IA 0.01 2 µA fSCLK = 0 (CS high) 5
Power Consumption, Normal Mode Active PWR 2.25 2.8 mW fSCLK = 3.2 MHz, fSMPL = 200 ksps, fIN = 20 kHz, CL = 15pF 5
Power Consumption, Shutdown PWR 0.06 11 µW fSCLK = 0 (CS high) 5
Maximum Clock Frequency fSCLK 3.2 4.8 MHz 5
Minimum Clock Frequency fSCLK 200 800 kHz 5
Maximum Sample Rate fS 200 300 ksps 5
Track/Hold Acquisition Time tACQ 1.5 2 SCLK cycles 5
Throughput Time tCYC 14 SCLK cycles Short cycled 6
Throughput Rate fRATE 200 ksps 6
SCLK Fall to CS Fall tCFCS 0 ns 6
CS Fall to SCLK Rise tCSCR 0 ns See (2) 6
SCLK Fall to Data Change Hold Time tCHLD 10 ns See (2) 6
SCLK Fall to Next DOUT Valid tCDV 38 100 ns 6
Rising Edge of CS To DOUT Disabled tDIS 38 50 ns 6
2nd SCLK Fall after CS Fall to DOUT Enabled tEN 6 50 ns 6
SCLK High Time tCH 60 42 ns 6
SCLK Low Time tCL 60 42 ns 6
DOUT Rise Time tr 5 50 ns 6
DOUT Fall Time tf 13 50 ns 6
Junction-to-Ambient Thermal Resistance θJA 20 °C/W 8-lead VSSOP 4

CAD (KiCad official)

  • Symbol: ADC121S625CIMMX
  • Footprint: Package_SO:VSSOP-8_2.3x2mm_P0.5mm
  • 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
  • 3D model files: adc121s625cimmx-etched.step / adc121s625cimmx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adc121s625cimmx.step / adc121s625cimmx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 a39e8529c6dffe0f, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF