# ADC12130CIWMX

**Texas Instruments** · Analog To Digital Converters (ADC) · SOIC-16

ADC12130CIWMX from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CH0 | input | Analog multiplexer input channel 0, selected by the DI address and not to exceed VA+ or go below GND. |
| 2 | CH1 | input | Analog multiplexer input channel 1, selected by the DI address and not to exceed VA+ or go below GND. |
| 3 | COM | input | Analog input used as a pseudo ground when the analog multiplexer is single-ended. |
| 4 | DOR | output | Data Output Ready, active push/pull output that is low while the conversion result is shifted out and goes high when all data has been shifted out. |
| 5 | EOC | output | End-of-conversion push/pull output that is low while the ADC is busy with a conversion, Auto Cal, Auto Zero or power down cycle and rises at the end of the cycle. |
| 6 | VREF- | power_in | Negative analog reference input that must not go below GND or exceed VREF+. |
| 7 | VREF+ | power_in | Positive analog reference input with VREF (VREF+ - VREF-) of 1.0 V to 5.0 V, not exceeding VA+. |
| 8 | DGND | power_in | Digital ground pin. |
| 9 | VA+ | power_in | Analog supply pin, 3.0 V to 5.5 V, tied to the same supply as VD+ and bypassed separately. |
| 10 | CONV | input | Active-low conversion/mode-programming control; a logic low is required to program any mode and high selects read-data-only mode with no new conversion. |
| 11 | CS | input | Active-low chip select; low enables DI shifting on SCLK rising edge and takes DO out of TRI-STATE, and a falling edge interrupts a conversion in progress. |
| 12 | DO | tri_state | Serial data output, push/pull when CS is low and TRI-STATE when CS is high, clocked out on the falling edge of SCLK. |
| 13 | DI | input | Serial data input shifted at the rising edge of SCLK into the multiplexer address and mode select register. |
| 14 | SCLK | input | Serial data clock input controlling serial data exchange rate, with rise and fall times not exceeding 1 us. |
| 15 | CCLK | input | Conversion clock input controlling the successive approximation conversion time and acquisition time, with rise and fall times not exceeding 1 us. |
| 16 | VD+ | power_in | Digital supply pin, 3.0 V to 5.5 V, tied to the same supply as VA+ and bypassed separately. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Data Acquisition |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `ADC12130CIWMX`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `adc12130ciwmx-etched.step` / `adc12130ciwmx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc12130ciwmx.step` / `adc12130ciwmx.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc12130) (53 pp, sha256 `a82068749df033f1`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/adc12130ciwmx-datasheet.pdf)