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ADC12020CIVYX
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Texas Instruments Analog To Digital Converters (ADC), TQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+68@@ -0,0 +1,68 @@+# ADC12020CIVYX++**Texas Instruments** · Analog To Digital Converters (ADC) · TQFP-32(7x7)++ADC12020CIVYX from Texas Instruments, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VREF | power_in | Reference input bypassed to AGND with a 0.1 µF monolithic capacitor, 2.0 V nominal and to be kept between 1.0 V and 2.2 V. |+| 2 | VIN+ | power_in | Non-inverting analog signal input; with a 2.0 V reference the differential input is 2.0 VP-P centered on VCM. |+| 3 | VIN− | power_in | Inverting analog signal input; with a 2.0 V reference the ground-referenced input is 2.0 VP-P centered on VCM, and it may be tied to VCM for single-ended operation although a differential input gives best performance. |+| 4 | AGND | power_in | Ground return for the analog supply. |+| 5 | VA | power_in | Positive analog supply, connected to a quiet +5 V source and bypassed to AGND with 0.1 µF and 10 µF capacitors within 1 cm of the pin. |+| 6 | VA | power_in | Positive analog supply, connected to a quiet +5 V source and bypassed to AGND with 0.1 µF and 10 µF capacitors within 1 cm of the pin. |+| 7 | AGND | power_in | Ground return for the analog supply. |+| 8 | PD | input | Power-down input; when high the converter enters power-down mode (about 40 mW), and when low the converter is active. |+| 9 | DGND | power_in | Ground return for the digital supply. |+| 10 | CLK | input | Digital clock input with a range of 100 kHz to 30 MHz (typical), specified at 20 MHz, sampled on its rising edge. |+| 11 | OE | input | Output enable; when low the TRI-STATE data outputs are enabled, and when high the outputs are in a high-impedance state. |+| 12 | DGND | power_in | Ground return for the digital supply. |+| 13 | VD | power_in | Positive digital supply, connected to the same quiet +5 V source as VA and bypassed to DGND with 0.1 µF in parallel with 10 µF within 1 cm of the pin. |+| 14 | D0 | tri_state | Digital data output, LSB of the 12-bit offset binary result, with TTL/CMOS compatible levels. |+| 15 | D1 | tri_state | Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels. |+| 16 | D2 | tri_state | Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels. |+| 17 | D3 | tri_state | Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels. |+| 18 | D4 | tri_state | Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels. |+| 19 | D5 | tri_state | Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels. |+| 20 | DR GND | power_in | Ground return for the output driver digital supply, to be connected to system digital ground and not in close proximity to the DGND or AGND pins. |+| 21 | VDR | power_in | Positive digital supply for the output drivers, operated from +2.35 V to +5 V (never above VD) and bypassed to DRGND with 0.1 µF. |+| 22 | D6 | tri_state | Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels. |+| 23 | D7 | tri_state | Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels. |+| 24 | D8 | tri_state | Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels. |+| 25 | D9 | tri_state | Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels. |+| 26 | D10 | tri_state | Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels. |+| 27 | D11 | tri_state | MSB of the 12-bit offset binary output word, with TTL/CMOS compatible levels. |+| 28 | AGND | power_in | Ground return for the analog supply. |+| 29 | VA | power_in | Positive analog supply, connected to a quiet +5 V source and bypassed to AGND with 0.1 µF and 10 µF capacitors within 1 cm of the pin. |+| 30 | VRN | passive | High-impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; do not load this pin. |+| 31 | VRP | passive | High-impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; do not load this pin. |+| 32 | VRM | passive | High-impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; do not load this pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-32(7x7) |+| Category | Data Acquisition |+| Pins | 32 |++## CAD (KiCad official)++- Symbol: `ADC12020CIVYX`+- Footprint: `Package_QFP:TQFP-32_7x7mm_P0.8mm`+- 3D model: TQFP-32(7x7) (KiCad packages3D, STEP)+- 3D model files: `adc12020civyx-etched.step` / `adc12020civyx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc12020civyx.step` / `adc12020civyx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc12020) (34 pp, sha256 `f2e8148bde22efb7`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adc12020civyx-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "adc12020civyx",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "adc12020civyx.kicad_sym",+ "adc12020civyx.kicad_mod",+ "adc12020civyx.glb",+ "adc12020civyx.step",+ "adc12020civyx.lbr",+ "docs/hero.png",+ "docs/adc12020civyx-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "adc12020civyx-hero.glb",+ "adc12020civyx-hero.overlay.json"+ ],+ "component": {+ "mpn": "ADC12020CIVYX",+ "manufacturer": "Texas Instruments",+ "package": "TQFP-32(7x7)",+ "pin_count": 32,+ "category": "Data Acquisition",+ "subcategory": "Analog To Digital Converters (ADC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/adc12020",+ "parts": {+ "symbol": "adc12020civyx.kicad_sym",+ "footprint": "adc12020civyx.kicad_mod",+ "model_3d": "adc12020civyx-hero.glb",+ "model_3d_plain": "adc12020civyx.glb",+ "model_3d_step": "adc12020civyx-etched.step",+ "model_3d_step_plain": "adc12020civyx.step",+ "lbr": "adc12020civyx.lbr"+ },+ "distributor_links": {+ "lcsc": "C2669933",+ "digikey": "ADC12020CIVYX-ND"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T21:05:19Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "ADC12020CIVYX-ND",+ "status": "found",+ "lifecycle": "Discontinued at DigiKey"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VREF",+ "type": "power_in",+ "description": "Reference input bypassed to AGND with a 0.1 µF monolithic capacitor, 2.0 V nominal and to be kept between 1.0 V and 2.2 V."+ },+ {+ "number": "2",+ "name": "VIN+",+ "type": "power_in",+ "description": "Non-inverting analog signal input; with a 2.0 V reference the differential input is 2.0 VP-P centered on VCM."+ },+ {+ "number": "3",+ "name": "VIN−",+ "type": "power_in",+ "description": "Inverting analog signal input; with a 2.0 V reference the ground-referenced input is 2.0 VP-P centered on VCM, and it may be tied to VCM for single-ended operation although a differential input gives best performance."+ },+ {+ "number": "4",+ "name": "AGND",+ "type": "power_in",+ "description": "Ground return for the analog supply."+ },+ {+ "number": "5",+ "name": "VA",+ "type": "power_in",+ "description": "Positive analog supply, connected to a quiet +5 V source and bypassed to AGND with 0.1 µF and 10 µF capacitors within 1 cm of the pin."+ },+ {+ "number": "6",+ "name": "VA",+ "type": "power_in",+ "description": "Positive analog supply, connected to a quiet +5 V source and bypassed to AGND with 0.1 µF and 10 µF capacitors within 1 cm of the pin."+ },+ {+ "number": "7",+ "name": "AGND",+ "type": "power_in",+ "description": "Ground return for the analog supply."+ },+ {+ "number": "8",+ "name": "PD",+ "type": "input",+ "description": "Power-down input; when high the converter enters power-down mode (about 40 mW), and when low the converter is active."+ },+ {+ "number": "9",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground return for the digital supply."+ },+ {+ "number": "10",+ "name": "CLK",+ "type": "input",+ "description": "Digital clock input with a range of 100 kHz to 30 MHz (typical), specified at 20 MHz, sampled on its rising edge."+ },+ {+ "number": "11",+ "name": "OE",+ "type": "input",+ "description": "Output enable; when low the TRI-STATE data outputs are enabled, and when high the outputs are in a high-impedance state."+ },+ {+ "number": "12",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground return for the digital supply."+ },+ {+ "number": "13",+ "name": "VD",+ "type": "power_in",+ "description": "Positive digital supply, connected to the same quiet +5 V source as VA and bypassed to DGND with 0.1 µF in parallel with 10 µF within 1 cm of the pin."+ },+ {+ "number": "14",+ "name": "D0",+ "type": "tri_state",+ "description": "Digital data output, LSB of the 12-bit offset binary result, with TTL/CMOS compatible levels."+ },+ {+ "number": "15",+ "name": "D1",+ "type": "tri_state",+ "description": "Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels."+ },+ {+ "number": "16",+ "name": "D2",+ "type": "tri_state",+ "description": "Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels."+ },+ {+ "number": "17",+ "name": "D3",+ "type": "tri_state",+ "description": "Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels."+ },+ {+ "number": "18",+ "name": "D4",+ "type": "tri_state",+ "description": "Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels."+ },+ {+ "number": "19",+ "name": "D5",+ "type": "tri_state",+ "description": "Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels."+ },+ {+ "number": "20",+ "name": "DR GND",+ "type": "power_in",+ "description": "Ground return for the output driver digital supply, to be connected to system digital ground and not in close proximity to the DGND or AGND pins."+ },+ {+ "number": "21",+ "name": "VDR",+ "type": "power_in",+ "description": "Positive digital supply for the output drivers, operated from +2.35 V to +5 V (never above VD) and bypassed to DRGND with 0.1 µF."+ },+ {+ "number": "22",+ "name": "D6",+ "type": "tri_state",+ "description": "Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels."+ },+ {+ "number": "23",+ "name": "D7",+ "type": "tri_state",+ "description": "Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels."+ },+ {+ "number": "24",+ "name": "D8",+ "type": "tri_state",+ "description": "Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels."+ },+ {+ "number": "25",+ "name": "D9",+ "type": "tri_state",+ "description": "Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels."+ },+ {+ "number": "26",+ "name": "D10",+ "type": "tri_state",+ "description": "Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels."+ },+ {+ "number": "27",+ "name": "D11",+ "type": "tri_state",+ "description": "MSB of the 12-bit offset binary output word, with TTL/CMOS compatible levels."+ },+ {+ "number": "28",+ "name": "AGND",+ "type": "power_in",+ "description": "Ground return for the analog supply."+ },+ {+ "number": "29",+ "name": "VA",+ "type": "power_in",+ "description": "Positive analog supply, connected to a quiet +5 V source and bypassed to AGND with 0.1 µF and 10 µF capacitors within 1 cm of the pin."+ },+ {+ "number": "30",+ "name": "VRN",+ "type": "passive",+ "description": "High-impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; do not load this pin."+ },+ {+ "number": "31",+ "name": "VRP",+ "type": "passive",+ "description": "High-impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; do not load this pin."+ },+ {+ "number": "32",+ "name": "VRM",+ "type": "passive",+ "description": "High-impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; do not load this pin."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The requested package hint is TQFP-32 (7x7), but the datasheet only documents a 32-lead LQFP (NEY003; The datasheet lists the data output pins only as the pin ranges 14-19 and 22-27 for D0-D11, without ; Pin 1 VREF is described as 1.0 V to 2.2 V in the pin description, while the Operating Ratings table ",+ "7/32 pins cited to the wrong page (name found elsewhere): ['15:D1@p4', '16:D2@p4', '17:D3@p4', '18:D4@p4']",+ "1/32 pin names appear NOWHERE in the datasheet text: ['24:D8@p4']"+ ],+ "pages_sent": 8,+ "cost_usd": 0.0676,+ "at": "2026-10-08T21:04:59"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/adc12020",+ "pages": 34,+ "sha256": "f2e8148bde22efb7",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 32,+ "described": 32,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "adc12020civyx.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "53431be61c684e9d923915676a90cb08050c23ee3f834d76a77a3b19b41422f1",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "adc12020civyx-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "21037f3c967637bf3ead60410340cded8c00375470bd2853e18f6685fd2386c8",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}