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ADC12020CIVYX

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Texas Instruments Analog To Digital Converters (ADC), TQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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ADC12020CIVYX

Texas Instruments · Analog To Digital Converters (ADC) · TQFP-32(7x7)

ADC12020CIVYX from Texas Instruments, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_in Reference input bypassed to AGND with a 0.1 µF monolithic capacitor, 2.0 V nominal and to be kept between 1.0 V and 2.2 V.
2 VIN+ power_in Non-inverting analog signal input; with a 2.0 V reference the differential input is 2.0 VP-P centered on VCM.
3 VIN− power_in Inverting analog signal input; with a 2.0 V reference the ground-referenced input is 2.0 VP-P centered on VCM, and it may be tied to VCM for single-ended operation although a differential input gives best performance.
4 AGND power_in Ground return for the analog supply.
5 VA power_in Positive analog supply, connected to a quiet +5 V source and bypassed to AGND with 0.1 µF and 10 µF capacitors within 1 cm of the pin.
6 VA power_in Positive analog supply, connected to a quiet +5 V source and bypassed to AGND with 0.1 µF and 10 µF capacitors within 1 cm of the pin.
7 AGND power_in Ground return for the analog supply.
8 PD input Power-down input; when high the converter enters power-down mode (about 40 mW), and when low the converter is active.
9 DGND power_in Ground return for the digital supply.
10 CLK input Digital clock input with a range of 100 kHz to 30 MHz (typical), specified at 20 MHz, sampled on its rising edge.
11 OE input Output enable; when low the TRI-STATE data outputs are enabled, and when high the outputs are in a high-impedance state.
12 DGND power_in Ground return for the digital supply.
13 VD power_in Positive digital supply, connected to the same quiet +5 V source as VA and bypassed to DGND with 0.1 µF in parallel with 10 µF within 1 cm of the pin.
14 D0 tri_state Digital data output, LSB of the 12-bit offset binary result, with TTL/CMOS compatible levels.
15 D1 tri_state Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels.
16 D2 tri_state Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels.
17 D3 tri_state Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels.
18 D4 tri_state Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels.
19 D5 tri_state Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels.
20 DR GND power_in Ground return for the output driver digital supply, to be connected to system digital ground and not in close proximity to the DGND or AGND pins.
21 VDR power_in Positive digital supply for the output drivers, operated from +2.35 V to +5 V (never above VD) and bypassed to DRGND with 0.1 µF.
22 D6 tri_state Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels.
23 D7 tri_state Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels.
24 D8 tri_state Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels.
25 D9 tri_state Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels.
26 D10 tri_state Digital data output bit of the 12-bit offset binary result, with TTL/CMOS compatible levels.
27 D11 tri_state MSB of the 12-bit offset binary output word, with TTL/CMOS compatible levels.
28 AGND power_in Ground return for the analog supply.
29 VA power_in Positive analog supply, connected to a quiet +5 V source and bypassed to AGND with 0.1 µF and 10 µF capacitors within 1 cm of the pin.
30 VRN passive High-impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; do not load this pin.
31 VRP passive High-impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; do not load this pin.
32 VRM passive High-impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; do not load this pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-32(7x7)
Category Data Acquisition
Pins 32

CAD (KiCad official)

  • Symbol: ADC12020CIVYX
  • Footprint: Package_QFP:TQFP-32_7x7mm_P0.8mm
  • 3D model: TQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: adc12020civyx-etched.step / adc12020civyx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adc12020civyx.step / adc12020civyx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 f2e8148bde22efb7, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF