component
ADC1175-50CIMTX
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 7h ago |
| viewers | 7h ago |
| adc1175-50cimtx-etched.glb | 7h ago |
| adc1175-50cimtx-etched.step | 7h ago |
| adc1175-50cimtx-hero.glb | 7h ago |
| adc1175-50cimtx-hero.overlay.json | 7h ago |
| adc1175-50cimtx.glb | 7h ago |
| adc1175-50cimtx.kicad_mod | 7h ago |
| adc1175-50cimtx.kicad_sym | 7h ago |
| adc1175-50cimtx.lbr | 7h ago |
| adc1175-50cimtx.step | 7h ago |
| package.json | 7h ago |
| page.json | 7h ago |
| README.md | 7h ago |
ADC1175-50CIMTX
Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-24
ADC1175-50CIMTX from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD | input | CMOS/TTL compatible power-down input; when high the device enters power-down with total power typically below 5 mW, and when low it operates normally. |
| 2 | DVSS | power_in | Ground return for the digital supply; connect to AVSS close to the ADC1175-50. |
| 3 | D0 | tri_state | Conversion data digital output, LSB; valid just after the CLK rising edge and high impedance when PD is low. |
| 4 | D1 | tri_state | Conversion data digital output bit 1; valid just after the CLK rising edge and high impedance when PD is low. |
| 5 | D2 | tri_state | Conversion data digital output bit 2; valid just after the CLK rising edge and high impedance when PD is low. |
| 6 | D3 | tri_state | Conversion data digital output bit 3; valid just after the CLK rising edge and high impedance when PD is low. |
| 7 | D4 | tri_state | Conversion data digital output bit 4; valid just after the CLK rising edge and high impedance when PD is low. |
| 8 | D5 | tri_state | Conversion data digital output bit 5; valid just after the CLK rising edge and high impedance when PD is low. |
| 9 | D6 | tri_state | Conversion data digital output bit 6; valid just after the CLK rising edge and high impedance when PD is low. |
| 10 | D7 | tri_state | Conversion data digital output, MSB; valid just after the CLK rising edge and high impedance when PD is low. |
| 11 | DVDD | power_in | Positive digital supply, +4.75 V to +5.25 V; share a common source with AVDD and bypass with 10 µF and 0.1 µF ceramic capacitors. |
| 12 | CLK | input | CMOS/TTL compatible clock input; VIN is sampled on the falling edge of CLK. |
| 13 | DVDD | power_in | Positive digital supply, +4.75 V to +5.25 V; share a common source with AVDD and bypass with 10 µF and 0.1 µF ceramic capacitors. |
| 14 | DVDD | power_in | Positive digital supply, +4.75 V to +5.25 V; share a common source with AVDD and bypass with 10 µF and 0.1 µF ceramic capacitors. |
| 15 | AVDD | power_in | Positive analog supply, +4.75 V to +5.25 V; share a common source with DVDD and bypass with 10 µF and 0.1 µF ceramic capacitors. |
| 16 | VRTS | passive | Reference top bias with internal pull-up resistor; short this pin to VRT to self-bias the reference ladder. |
| 17 | VRT | input | Analog input for the high (top) side of the reference ladder, range 1.0 V to VDD; it defines the VIN conversion range together with VRB and must be bypassed well. |
| 18 | AVDD | power_in | Positive analog supply, +4.75 V to +5.25 V; share a common source with DVDD and bypass with 10 µF and 0.1 µF ceramic capacitors. |
| 19 | VIN | power_in | Analog signal input; conversion range is VRB to VRT. |
| 20 | AVSS | power_in | Ground return for the analog supply; connect to DVSS close to the ADC1175-50 package. |
| 21 | AVSS | power_in | Ground return for the analog supply; connect to DVSS close to the ADC1175-50 package. |
| 22 | VRBS | passive | Reference bottom bias with internal pull-down resistor; short to VRB to self-bias the reference ladder, and bypass well unless grounded. |
| 23 | VRB | input | Analog input for the low (bottom) side of the reference ladder, nominal range 0.0 V to 4.0 V with optimized value 0.6 V; it defines the VIN conversion range together with VRT and must be bypassed well. |
| 24 | DVSS | power_in | Ground return for the digital supply; connect to AVSS close to the ADC1175-50. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-24 |
| Category | Data Acquisition |
| Pins | 24 |
CAD (KiCad official)
- Symbol:
ADC1175-50CIMTX - Footprint:
Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm - 3D model: TSSOP-24 (KiCad packages3D, STEP)
- 3D model files:
adc1175-50cimtx-etched.step/adc1175-50cimtx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adc1175-50cimtx.step/adc1175-50cimtx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
57da6210a3bd954b, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).