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ADC1175-50CIMTX
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Texas Instruments Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+60@@ -0,0 +1,60 @@+# ADC1175-50CIMTX++**Texas Instruments** · Analog To Digital Converters (ADC) · TSSOP-24++ADC1175-50CIMTX from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PD | input | CMOS/TTL compatible power-down input; when high the device enters power-down with total power typically below 5 mW, and when low it operates normally. |+| 2 | DVSS | power_in | Ground return for the digital supply; connect to AVSS close to the ADC1175-50. |+| 3 | D0 | tri_state | Conversion data digital output, LSB; valid just after the CLK rising edge and high impedance when PD is low. |+| 4 | D1 | tri_state | Conversion data digital output bit 1; valid just after the CLK rising edge and high impedance when PD is low. |+| 5 | D2 | tri_state | Conversion data digital output bit 2; valid just after the CLK rising edge and high impedance when PD is low. |+| 6 | D3 | tri_state | Conversion data digital output bit 3; valid just after the CLK rising edge and high impedance when PD is low. |+| 7 | D4 | tri_state | Conversion data digital output bit 4; valid just after the CLK rising edge and high impedance when PD is low. |+| 8 | D5 | tri_state | Conversion data digital output bit 5; valid just after the CLK rising edge and high impedance when PD is low. |+| 9 | D6 | tri_state | Conversion data digital output bit 6; valid just after the CLK rising edge and high impedance when PD is low. |+| 10 | D7 | tri_state | Conversion data digital output, MSB; valid just after the CLK rising edge and high impedance when PD is low. |+| 11 | DVDD | power_in | Positive digital supply, +4.75 V to +5.25 V; share a common source with AVDD and bypass with 10 µF and 0.1 µF ceramic capacitors. |+| 12 | CLK | input | CMOS/TTL compatible clock input; VIN is sampled on the falling edge of CLK. |+| 13 | DVDD | power_in | Positive digital supply, +4.75 V to +5.25 V; share a common source with AVDD and bypass with 10 µF and 0.1 µF ceramic capacitors. |+| 14 | DVDD | power_in | Positive digital supply, +4.75 V to +5.25 V; share a common source with AVDD and bypass with 10 µF and 0.1 µF ceramic capacitors. |+| 15 | AVDD | power_in | Positive analog supply, +4.75 V to +5.25 V; share a common source with DVDD and bypass with 10 µF and 0.1 µF ceramic capacitors. |+| 16 | VRTS | passive | Reference top bias with internal pull-up resistor; short this pin to VRT to self-bias the reference ladder. |+| 17 | VRT | input | Analog input for the high (top) side of the reference ladder, range 1.0 V to VDD; it defines the VIN conversion range together with VRB and must be bypassed well. |+| 18 | AVDD | power_in | Positive analog supply, +4.75 V to +5.25 V; share a common source with DVDD and bypass with 10 µF and 0.1 µF ceramic capacitors. |+| 19 | VIN | power_in | Analog signal input; conversion range is VRB to VRT. |+| 20 | AVSS | power_in | Ground return for the analog supply; connect to DVSS close to the ADC1175-50 package. |+| 21 | AVSS | power_in | Ground return for the analog supply; connect to DVSS close to the ADC1175-50 package. |+| 22 | VRBS | passive | Reference bottom bias with internal pull-down resistor; short to VRB to self-bias the reference ladder, and bypass well unless grounded. |+| 23 | VRB | input | Analog input for the low (bottom) side of the reference ladder, nominal range 0.0 V to 4.0 V with optimized value 0.6 V; it defines the VIN conversion range together with VRT and must be bypassed well. |+| 24 | DVSS | power_in | Ground return for the digital supply; connect to AVSS close to the ADC1175-50. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-24 |+| Category | Data Acquisition |+| Pins | 24 |++## CAD (KiCad official)++- Symbol: `ADC1175-50CIMTX`+- Footprint: `Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm`+- 3D model: TSSOP-24 (KiCad packages3D, STEP)+- 3D model files: `adc1175-50cimtx-etched.step` / `adc1175-50cimtx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc1175-50cimtx.step` / `adc1175-50cimtx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc1175-50) (28 pp, sha256 `57da6210a3bd954b`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adc1175-50cimtx-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "adc1175-50cimtx",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "adc1175-50cimtx.kicad_sym",+ "adc1175-50cimtx.kicad_mod",+ "adc1175-50cimtx.glb",+ "adc1175-50cimtx.step",+ "adc1175-50cimtx.lbr",+ "docs/hero.png",+ "docs/adc1175-50cimtx-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "adc1175-50cimtx-hero.glb",+ "adc1175-50cimtx-hero.overlay.json"+ ],+ "component": {+ "mpn": "ADC1175-50CIMTX",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-24",+ "pin_count": 24,+ "category": "Data Acquisition",+ "subcategory": "Analog To Digital Converters (ADC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/adc1175-50",+ "parts": {+ "symbol": "adc1175-50cimtx.kicad_sym",+ "footprint": "adc1175-50cimtx.kicad_mod",+ "model_3d": "adc1175-50cimtx-hero.glb",+ "model_3d_plain": "adc1175-50cimtx.glb",+ "model_3d_step": "adc1175-50cimtx-etched.step",+ "model_3d_step_plain": "adc1175-50cimtx.step",+ "lbr": "adc1175-50cimtx.lbr"+ },+ "distributor_links": {+ "lcsc": "C91171",+ "digikey": "ADC1175-50CIMTX-ND",+ "mouser": "926-ADC1175-50CIMTX"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:55:48Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "ADC1175-50CIMTX-ND",+ "status": "found",+ "lifecycle": "Obsolete"+ },+ "mouser": {+ "pn": "926-ADC1175-50CIMTX",+ "status": "found",+ "lifecycle": "Obsolete"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "PD",+ "type": "input",+ "description": "CMOS/TTL compatible power-down input; when high the device enters power-down with total power typically below 5 mW, and when low it operates normally."+ },+ {+ "number": "2",+ "name": "DVSS",+ "type": "power_in",+ "description": "Ground return for the digital supply; connect to AVSS close to the ADC1175-50."+ },+ {+ "number": "3",+ "name": "D0",+ "type": "tri_state",+ "description": "Conversion data digital output, LSB; valid just after the CLK rising edge and high impedance when PD is low."+ },+ {+ "number": "4",+ "name": "D1",+ "type": "tri_state",+ "description": "Conversion data digital output bit 1; valid just after the CLK rising edge and high impedance when PD is low."+ },+ {+ "number": "5",+ "name": "D2",+ "type": "tri_state",+ "description": "Conversion data digital output bit 2; valid just after the CLK rising edge and high impedance when PD is low."+ },+ {+ "number": "6",+ "name": "D3",+ "type": "tri_state",+ "description": "Conversion data digital output bit 3; valid just after the CLK rising edge and high impedance when PD is low."+ },+ {+ "number": "7",+ "name": "D4",+ "type": "tri_state",+ "description": "Conversion data digital output bit 4; valid just after the CLK rising edge and high impedance when PD is low."+ },+ {+ "number": "8",+ "name": "D5",+ "type": "tri_state",+ "description": "Conversion data digital output bit 5; valid just after the CLK rising edge and high impedance when PD is low."+ },+ {+ "number": "9",+ "name": "D6",+ "type": "tri_state",+ "description": "Conversion data digital output bit 6; valid just after the CLK rising edge and high impedance when PD is low."+ },+ {+ "number": "10",+ "name": "D7",+ "type": "tri_state",+ "description": "Conversion data digital output, MSB; valid just after the CLK rising edge and high impedance when PD is low."+ },+ {+ "number": "11",+ "name": "DVDD",+ "type": "power_in",+ "description": "Positive digital supply, +4.75 V to +5.25 V; share a common source with AVDD and bypass with 10 µF and 0.1 µF ceramic capacitors."+ },+ {+ "number": "12",+ "name": "CLK",+ "type": "input",+ "description": "CMOS/TTL compatible clock input; VIN is sampled on the falling edge of CLK."+ },+ {+ "number": "13",+ "name": "DVDD",+ "type": "power_in",+ "description": "Positive digital supply, +4.75 V to +5.25 V; share a common source with AVDD and bypass with 10 µF and 0.1 µF ceramic capacitors."+ },+ {+ "number": "14",+ "name": "DVDD",+ "type": "power_in",+ "description": "Positive digital supply, +4.75 V to +5.25 V; share a common source with AVDD and bypass with 10 µF and 0.1 µF ceramic capacitors."+ },+ {+ "number": "15",+ "name": "AVDD",+ "type": "power_in",+ "description": "Positive analog supply, +4.75 V to +5.25 V; share a common source with DVDD and bypass with 10 µF and 0.1 µF ceramic capacitors."+ },+ {+ "number": "16",+ "name": "VRTS",+ "type": "passive",+ "description": "Reference top bias with internal pull-up resistor; short this pin to VRT to self-bias the reference ladder."+ },+ {+ "number": "17",+ "name": "VRT",+ "type": "input",+ "description": "Analog input for the high (top) side of the reference ladder, range 1.0 V to VDD; it defines the VIN conversion range together with VRB and must be bypassed well."+ },+ {+ "number": "18",+ "name": "AVDD",+ "type": "power_in",+ "description": "Positive analog supply, +4.75 V to +5.25 V; share a common source with DVDD and bypass with 10 µF and 0.1 µF ceramic capacitors."+ },+ {+ "number": "19",+ "name": "VIN",+ "type": "power_in",+ "description": "Analog signal input; conversion range is VRB to VRT."+ },+ {+ "number": "20",+ "name": "AVSS",+ "type": "power_in",+ "description": "Ground return for the analog supply; connect to DVSS close to the ADC1175-50 package."+ },+ {+ "number": "21",+ "name": "AVSS",+ "type": "power_in",+ "description": "Ground return for the analog supply; connect to DVSS close to the ADC1175-50 package."+ },+ {+ "number": "22",+ "name": "VRBS",+ "type": "passive",+ "description": "Reference bottom bias with internal pull-down resistor; short to VRB to self-bias the reference ladder, and bypass well unless grounded."+ },+ {+ "number": "23",+ "name": "VRB",+ "type": "input",+ "description": "Analog input for the low (bottom) side of the reference ladder, nominal range 0.0 V to 4.0 V with optimized value 0.6 V; it defines the VIN conversion range together with VRT and must be bypassed well."+ },+ {+ "number": "24",+ "name": "DVSS",+ "type": "power_in",+ "description": "Ground return for the digital supply; connect to AVSS close to the ADC1175-50."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet pin tables list TSSOP pin numbers with WQFN numbers in parentheses. The TSSOP numbers ; The datasheet does not give a KiCad ERC class for analog pins. VIN, VRT and VRB were typed as input,; Supply pin descriptions use the +4.75 V to +5.25 V operating supply range from the Operating Ratings",+ "3/24 pins cited to the wrong page (name found elsewhere): ['6:D3@p4', '7:D4@p4', '8:D5@p4']"+ ],+ "pages_sent": 8,+ "cost_usd": 0.0634,+ "at": "2026-10-08T18:55:10"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/adc1175-50",+ "pages": 28,+ "sha256": "57da6210a3bd954b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 24,+ "described": 24,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "adc1175-50cimtx.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "706322f42d9793ebf28d5b80100a68bfa8769998a00b78acadf7af937fc1454f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "adc1175-50cimtx-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "56058f029e61ba2b7d9a6778c79b7b40fa0b367f0a7550b570b98f1ddc114327",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}