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ADC108S052CIMTX
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Texas Instruments Analog To Digital Converters (ADCs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADC108S052CIMTX
Texas Instruments · Analog To Digital Converters (ADCs) · TSSOP-16
ADC108S052CIMTX from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip select: a conversion begins on the falling edge of CS and conversions continue as long as CS is held low. |
| 2 | VA | power_in | Positive analog supply, connected to a quiet +2.7 V to +5.25 V source and also used as the reference voltage; bypass to GND with 1 µF and 0.1 µF monolithic ceramic capacitors within 1 cm of the pin. |
| 3 | AGND | power_in | Ground return for the analog supply and signals. |
| 4 | IN0 | input | Analog input channel 0, with signal range 0 V to VREF. |
| 5 | IN1 | input | Analog input channel 1, with signal range 0 V to VREF. |
| 6 | IN2 | input | Analog input channel 2, with signal range 0 V to VREF. |
| 7 | IN3 | input | Analog input channel 3, with signal range 0 V to VREF. |
| 8 | IN4 | input | Analog input channel 4, with signal range 0 V to VREF. |
| 9 | IN5 | input | Analog input channel 5, with signal range 0 V to VREF. |
| 10 | IN6 | input | Analog input channel 6, with signal range 0 V to VREF. |
| 11 | IN7 | input | Analog input channel 7, with signal range 0 V to VREF. |
| 12 | DGND | power_in | Ground return for the digital supply and signals. |
| 13 | VD | power_in | Positive digital supply, connected to a +2.7 V to VA source and bypassed to GND with a 0.1 µF monolithic ceramic capacitor within 1 cm of the pin. |
| 14 | DIN | input | Digital data input; the Control Register is loaded through this pin on rising edges of SCLK. |
| 15 | DOUT | output | Digital data output; output samples are clocked out on the falling edges of SCLK. |
| 16 | SCLK | input | Digital clock input with a specified performance range of 3.2 MHz to 8 MHz, which directly controls the conversion and readout processes. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Supply Voltage | VA | -0.3 | 6.5 | V | 3 | ||
| Digital Supply Voltage | VD | -0.3 | 6.5 | V | upper limit VA + 0.3V, max 6.5V | 3 | |
| Voltage on Any Pin to GND | -0.3 | V | upper limit VA + 0.3V | 3 | |||
| Input Current at Any Pin | -10 | 10 | mA | 3 | |||
| Package Input Current | -20 | 20 | mA | 3 | |||
| Junction Temperature | 150 | °C | 3 | ||||
| Storage Temperature | -65 | 150 | °C | 3 | |||
| ESD Susceptibility | 2500 | V | Human body model | 3 | |||
| ESD Susceptibility | 250 | V | Machine model | 3 | |||
| Operating Temperature | TA | -40 | 105 | °C | 3 | ||
| VA Supply Voltage | VA | 2.7 | 5.25 | V | 3 | ||
| VD Supply Voltage | VD | 2.7 | V | upper limit VA | 3 | ||
| Digital Input Voltage | 0 | V | upper limit VA | 3 | |||
| Analog Input Voltage | 0 | V | upper limit VA | 3 | |||
| Clock Frequency | 50 | kHz | 3 | ||||
| Clock Frequency | 16 | MHz | 3 | ||||
| Integral Non-Linearity (End Point Method) | INL | -0.4 | 0.1 | 0.4 | LSB | 4 | |
| Differential Non-Linearity | DNL | -0.4 | 0.2 | 0.4 | LSB | 4 | |
| Offset Error | VOFF | -0.7 | 0.3 | 0.7 | LSB | 4 | |
| Offset Error Match | OEM | -0.4 | 0.06 | 0.4 | LSB | 4 | |
| Full Scale Error | FSE | -0.4 | 0.1 | 0.4 | LSB | 4 | |
| Full Scale Error Match | FSEM | -0.4 | 0.06 | 0.4 | LSB | 4 | |
| Signal-to-Noise Plus Distortion Ratio | SINAD | 61.3 | 61.8 | dB | fIN = 40.2 kHz, −0.02 dBFS | 4 | |
| Signal-to-Noise Ratio | SNR | 61.4 | 61.8 | dB | fIN = 40.2 kHz, −0.02 dBFS | 4 | |
| Total Harmonic Distortion | THD | -87.4 | -74.5 | dB | fIN = 40.2 kHz, −0.02 dBFS | 4 | |
| Spurious-Free Dynamic Range | SFDR | 76 | 83.2 | dB | fIN = 40.2 kHz, −0.02 dBFS | 4 | |
| Effective Number of Bits | ENOB | 9.89 | 9.98 | Bits | fIN = 40.2 kHz | 4 | |
| Input Range | VIN | 0 | V | 4 | |||
| DC Leakage Current | IDCL | -1 | 1 | µA | 4 | ||
| Input High Voltage | VIH | 2.1 | V | VA = VD = +2.7V to +3.6V | 4 | ||
| Input High Voltage | VIH | 2.4 | V | VA = VD = +4.75V to +5.25V | 4 | ||
| Input Low Voltage | VIL | 0.8 | V | 4 | |||
| Input Current | IIN | -1 | 0.01 | 1 | µA | VIN = 0V or VD | 4 |
| Digital Input Capacitance | CIND | 2 | 4 | pF | 4 | ||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 200 µA to 1.0 mA | 4 | ||
| Hi-Impedance Output Leakage Current | IOZH, IOZL | -1 | 1 | µA | 4 | ||
| Hi-Impedance Output Capacitance | COUT | 2 | 4 | pF | 4 | ||
| Analog and Digital Supply Voltages | VA, VD | 2.7 | 5.25 | V | VA ≥ VD | 5 | |
| Total Supply Current, Normal Mode (CS low) | IA + ID | 0.49 | 1.1 | mA | VA = VD = +2.7V to +3.6V, fSAMPLE = 500 kSPS, fIN = 40 kHz | 5 | |
| Total Supply Current, Normal Mode (CS low) | IA + ID | 1.5 | 2.4 | mA | VA = VD = +4.75V to +5.25V, fSAMPLE = 500 kSPS, fIN = 40 kHz | 5 | |
| Power Consumption, Normal Mode (CS low) | PC | 1.5 | 3.3 | mW | VA = VD = +3.0V, fSAMPLE = 500 kSPS, fIN = 40 kHz | 5 | |
| Power Consumption, Normal Mode (CS low) | PC | 7.5 | 12.1 | mW | VA = VD = +5.0V, fSAMPLE = 500 kSPS, fIN = 40 kHz | 5 | |
| Minimum Clock Frequency | fSCLKMIN | 3.2 | 0.8 | MHz | 5 | ||
| Maximum Clock Frequency | fSCLK | 16 | 8 | MHz | 5 | ||
| Sample Rate | 200 | 50 | ksps | 5 | |||
| Sample Rate, Continuous Mode | fS | 1000 | 500 | ksps | Continuous mode | 5 | |
| SCLK Duty Cycle | DC | 40 | 30 | % | 5 | ||
| SCLK Duty Cycle | DC | 70 | 60 | % | 5 | ||
| CS Hold Time after SCLK Rising Edge | tCSH | 10 | 0 | ns | 6 | ||
| CS Setup Time prior to SCLK Rising Edge | tCSS | 10 | 5 | ns | 6 | ||
| CS Falling Edge to DOUT enabled | tEN | 5 | 30 | ns | 6 | ||
| DOUT Access Time after SCLK Falling Edge | tDACC | 17 | 27 | ns | 6 | ||
| DIN Setup Time prior to SCLK Rising Edge | tDS | 10 | 3 | ns | 6 | ||
| DIN Hold Time after SCLK Rising Edge | tDH | 10 | 3 | ns | 6 | ||
| CS Rising Edge to DOUT High-Impedance | tDIS | 2.4 | 20 | ns | DOUT falling | 6 | |
| CS Rising Edge to DOUT High-Impedance | tDIS | 0.9 | 20 | ns | DOUT rising | 6 | |
| Package Thermal Resistance, Junction-to-Ambient | θJA | 96 | °C / W | 16-lead TSSOP on 4-layer, 2 oz. PCB | 3 |
CAD (KiCad official)
- Symbol:
ADC108S052CIMTX - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
adc108s052cimtx-etched.step/adc108s052cimtx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adc108s052cimtx.step/adc108s052cimtx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
710debd97aa5ceb0, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).