component
ADC102S021CIMM
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
ADC102S021CIMM
Texas Instruments · Analog To Digital Converters (ADC) · VSSOP-8
ADC102S021CIMM from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip select: a conversion process begins on the falling edge of CS and continues as long as CS is held low. |
| 2 | VA | power_in | Positive supply pin, specified for +2.7 V to +5.25 V, to be bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. |
| 3 | GND | power_in | Ground return for the die. |
| 4 | IN2 | input | Analog input that can range from 0 V to VA. |
| 5 | IN1 | input | Analog input that can range from 0 V to VA. |
| 6 | DIN | input | Digital data input through which the Control Register is loaded on rising edges of SCLK; digital input voltage range is −0.3 V to VA. |
| 7 | DOUT | output | Digital data output; output samples are clocked out of this pin on falling edges of SCLK. |
| 8 | SCLK | input | Digital clock input that directly controls the conversion and readout processes. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8 |
| Category | Data Acquisition |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
ADC102S021CIMM - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
adc102s021cimm-etched.step/adc102s021cimm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adc102s021cimm.step/adc102s021cimm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
646f63f9ba66b44e, retrieved 2026-10-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADC102S021CIMM
**Texas Instruments** · Analog To Digital Converters (ADC) · VSSOP-8
ADC102S021CIMM from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip select: a conversion process begins on the falling edge of CS and continues as long as CS is held low. |
| 2 | VA | power_in | Positive supply pin, specified for +2.7 V to +5.25 V, to be bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. |
| 3 | GND | power_in | Ground return for the die. |
| 4 | IN2 | input | Analog input that can range from 0 V to VA. |
| 5 | IN1 | input | Analog input that can range from 0 V to VA. |
| 6 | DIN | input | Digital data input through which the Control Register is loaded on rising edges of SCLK; digital input voltage range is −0.3 V to VA. |
| 7 | DOUT | output | Digital data output; output samples are clocked out of this pin on falling edges of SCLK. |
| 8 | SCLK | input | Digital clock input that directly controls the conversion and readout processes. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8 |
| Category | Data Acquisition |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `ADC102S021CIMM`
- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`
- 3D model: VSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `adc102s021cimm-etched.step` / `adc102s021cimm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc102s021cimm.step` / `adc102s021cimm.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc102s021) (28 pp, sha256 `646f63f9ba66b44e`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adc102s021cimm-datasheet.pdf)