ADC101S101CIMFX from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VA	power_in	Positive supply pin that should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin.
2	GND	power_in	The ground return for the supply and signals.
3	VIN	power_in	Analog input that can range from 0V to VA.
4	SCLK	input	Digital clock input that directly controls the conversion and readout processes.
5	SDATA	output	Digital data output; the output samples are clocked out of this pin on falling edges of the SCLK pin.
6	CS	input	Chip select; on the falling edge of CS, a conversion process begins.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOT-23-6
Category	Data Acquisition
Pins	6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog Supply Voltage	VA	2.7		5.25	V		4
Operating Temperature Range	TA	-40		85	°C		3
Digital Input Pins Voltage Range		-0.3		5.25	V	regardless of supply voltage	3
Sample Rate	fS			1	Msps	up to 1 Msps	3
Analog Supply Voltage absolute max	VA	-0.3		6.5	V		3
Voltage on Any Pin to GND		-0.3			V	max is (VA +0.3) V	3
Input Current at Any Pin		-10		10	mA	±10 mA	3
Package Input Current		-20		20	mA	±20 mA	3
ESD Human Body Model				3500	V		3
ESD Machine Model				300	V		3
Junction Temperature	TJ			150	°C		3
Storage Temperature	TSTG	-65		150	°C		3
Package Thermal Resistance junction-to-ambient	θJA		265		°C/W	6-lead SOT-23	3
Integral Non-Linearity	INL		0.2	0.7	LSB	VA = +2.7V to +5.25V	4
Differential Non-Linearity max	DNL			0.3	LSB	VA = +2.7V to +5.25V	4
Differential Non-Linearity min	DNL	-0.2			LSB	VA = +2.7V to +5.25V	4
Offset Error	VOFF		0.1	0.7	LSB	VA = +2.7V to +5.25V	4
Gain Error	GE	-1	0.2		LSB	VA = +2.7V to +5.25V	4
Signal-to-Noise Plus Distortion Ratio	SINAD	61	61.7		dB	VA = +2.7 to 5.25V, fIN = 100 kHz, −0.02 dBFS	4
Signal-to-Noise Ratio	SNR	61.2	62		dB	VA = +2.7 to 5.25V, fIN = 100 kHz, −0.02 dBFS	4
Total Harmonic Distortion	THD		-77	-73	dB	VA = +2.7 to 5.25V, fIN = 100 kHz, −0.02 dBFS	4
Spurious-Free Dynamic Range	SFDR	74	78		dB	VA = +2.7 to 5.25V, fIN = 100 kHz, −0.02 dBFS	4
Effective Number of Bits	ENOB	9.8	9.9		Bits	VA = +2.7 to 5.25V, fIN = 100 kHz, −0.02 dBFS	4
DC Leakage Current	IDCL			1	µA		4
Input High Voltage	VIH	2.4			V	VA = +5.25V	4
Input High Voltage	VIH	2.1			V	VA = +3.6V	4
Input Low Voltage	VIL			0.8	V	VA = +5V	4
Input Low Voltage	VIL			0.4	V	VA = +3V	4
Input Current	IIN		0.1	1	µA	VIN = 0V or VA	4
Digital Input Capacitance	CIND		2	4	pF		4
Output Low Voltage	VOL		0.03	0.4	V	ISINK = 200 µA	4
TRI-STATE Leakage Current	IOZH, IOZL		0.1	10	µA		4
TRI-STATE Output Capacitance	COUT		2	4	pF		4
Input Capacitance Track Mode	CINA		30		pF	Track Mode	4
Supply Voltage	VA	2.7		5.25	V		5
Supply Current, Normal Mode SOT-23	IA		3.2	2	mA	VA = +5.25V, fSAMPLE = 1 Msps	5
Supply Current, Normal Mode SOT-23	IA		1.5	0.6	mA	VA = +3.6V, fSAMPLE = 1 Msps	5
Power Consumption, Normal Mode SOT-23	PD		16	10	mW	VA = +5V	5
Power Consumption, Normal Mode SOT-23	PD		4.5	2	mW	VA = +3V	5
SCLK Clock Frequency	fSCLK	10		20	MHz		5
SCLK Duty Cycle	DC	40	50	60	%	fSCLK = 20 MHz	5
Minimum Time Required for Acquisition	tACQ			350	ns		5
Minimum Quiet Time	tQUIET	50			ns		5
Minimum CS Pulse Width	tCS	10			ns		6
CS to SCLK Setup Time	tSU	10			ns		6
Delay from CS Until SDATA TRI-STATE Disabled	tEN			20	ns		6
Data Access Time after SCLK Falling Edge	tACC			40	ns	VA = +2.7 to +3.6	6
Data Access Time after SCLK Falling Edge	tACC			20	ns	VA = +4.75 to +5.25	6
SCLK to Data Valid Hold Time	tH	7			ns	VA = +2.7 to +3.6	6
SCLK to Data Valid Hold Time	tH	5			ns	VA = +4.75 to +5.25	6
SCLK Falling Edge to SDATA High Impedance	tDIS	6		25	ns	VA = +2.7 to +3.6	6
SCLK Falling Edge to SDATA High Impedance	tDIS	5		25	ns	VA = +4.75 to +5.25	6

CAD (KiCad official)

Symbol: ADC101S101CIMFX
Footprint: Package_TO_SOT_SMD:SOT-23-6
3D model: SOT-23-6 (KiCad packages3D, STEP)
3D model files: adc101s101cimfx-etched.step / adc101s101cimfx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adc101s101cimfx.step / adc101s101cimfx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (25 pp, sha256 62570dbe3c680410, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADC101S101CIMFX

Verified ADC101S101CIMFX

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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