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ADC088S022CIMTX

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Texas Instruments Analog To Digital Converters (ADCs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADC088S022CIMTX

Texas Instruments · Analog To Digital Converters (ADCs) · TSSOP-16

ADC088S022CIMTX from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip select; a conversion begins on the falling edge of CS and conversions continue as long as CS is held low.
2 VA power_in Positive analog supply and reference voltage, to be connected to a quiet +2.7V to +5.25V source and bypassed to GND with 1 µF and 0.1 µF monolithic ceramic capacitors within 1 cm of the pin.
3 AGND power_in Ground return for the analog supply and signals.
4 IN0 input Analog input 0, which can range from 0V to VREF.
5 IN1 input Analog input 1, which can range from 0V to VREF.
6 IN2 input Analog input 2, which can range from 0V to VREF.
7 IN3 input Analog input 3, which can range from 0V to VREF.
8 IN4 input Analog input 4, which can range from 0V to VREF.
9 IN5 input Analog input 5, which can range from 0V to VREF.
10 IN6 input Analog input 6, which can range from 0V to VREF.
11 IN7 input Analog input 7, which can range from 0V to VREF.
12 DGND power_in Ground return for the digital supply and signals.
13 VD power_in Positive digital supply, to be connected to a +2.7V to VA supply and bypassed to GND with a 0.1 µF monolithic ceramic capacitor within 1 cm of the pin.
14 DIN input Digital data input through which the Control Register is loaded on rising edges of SCLK.
15 DOUT output Digital data output; output samples are clocked out on the falling edges of SCLK.
16 SCLK input Digital clock input with a specified frequency range of 0.8 MHz to 3.2 MHz that directly controls the conversion and readout processes.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Data Converters
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Integral Non-Linearity INL -0.2 0.04 0.2 LSB VA = VD = +2.7V to +5.25V 4
Differential Non-Linearity DNL -0.2 0.04 0.2 LSB VA = VD = +2.7V to +5.25V 4
Offset Error VOFF -0.7 0.6 0.7 LSB 4
Offset Error Match OEM -0.2 0.02 0.2 LSB 4
Full Scale Error FSE -0.6 0.5 0.6 LSB 4
Full Scale Error Match FSEM -0.2 0.02 0.2 LSB 4
Signal-to-Noise Plus Distortion Ratio SINAD 49.2 49.5 dB fIN = 39.9 kHz, -0.02 dBFS 4
Signal-to-Noise Ratio SNR 49.2 49.5 dB fIN = 39.9 kHz, -0.02 dBFS 4
Total Harmonic Distortion THD -70.1 -56.8 dB fIN = 39.9 kHz, -0.02 dBFS 4
Spurious-Free Dynamic Range SFDR 64.2 67.7 dB fIN = 39.9 kHz, -0.02 dBFS 4
Effective Number of Bits ENOB 7.88 7.93 Bits fIN = 39.9 kHz 4
DC Leakage Current IDCL -1 1 µA 4
Input High Voltage VIH 2.1 V VA = VD = +2.7V to +3.6V 4
Input High Voltage VIH 2.4 V VA = VD = +4.75V to +5.25V 4
Input Low Voltage VIL 0.8 V 4
Input Current IIN -1 0.01 1 µA VIN = 0V or VD 4
Digital Input Capacitance CIND 2 4 pF 4
Output Low Voltage VOL 0.4 V ISINK = 200 µA to 1.0 mA 4
Hi-Impedance Output Leakage Current IOZH, IOZL -1 1 µA 4
Hi-Impedance Output Capacitance COUT 2 4 pF 4
Analog and Digital Supply Voltages VA, VD 2.7 5.25 V VA ≥ VD 5
Total Supply Current Normal Mode IA + ID 0.3 0.74 mA VA = VD = +2.7V to +3.6V, fSAMPLE = 200 kSPS, fIN = 40 kHz 5
Total Supply Current Normal Mode IA + ID 1.1 1.55 mA VA = VD = +4.75V to +5.25V, fSAMPLE = 200 kSPS, fIN = 40 kHz 5
Power Consumption Normal Mode PC 0.9 2.2 mW VA = VD = +3.0V, fSAMPLE = 200 kSPS, fIN = 40 kHz 5
Power Consumption Normal Mode PC 5.5 7.8 mW VA = VD = +5.0V, fSAMPLE = 200 kSPS, fIN = 40 kHz 5
Minimum Clock Frequency fSCLKMIN 0.8 MHz 5
Maximum Clock Frequency fSCLK 16 3.2 MHz 5
Sample Rate Continuous Mode fS 50 1000 200 ksps 5
SCLK Duty Cycle DC 40 50 60 % 5
CS Hold Time after SCLK Rising Edge tCSH 10 0 ns 5
CS Setup Time prior to SCLK Rising Edge tCSS 10 5 ns 5
CS Falling Edge to DOUT enabled tEN 5 30 ns 5
DOUT Access Time after SCLK Falling Edge tDACC 17 27 ns 5
DIN Setup Time prior to SCLK Rising Edge tDS 10 3 ns 5
DIN Hold Time after SCLK Rising Edge tDH 10 3 ns 5
CS Rising Edge to DOUT High-Impedance tDIS 2.4 20 ns DOUT falling 5
CS Rising Edge to DOUT High-Impedance tDIS 0.9 20 ns DOUT rising 5
Analog Supply Voltage VA -0.3 6.5 V 3
Digital Supply Voltage VD -0.3 6.5 V -0.3V to VA + 0.3V, max 6.5V 3
Voltage on Any Pin to GND -0.3 V -0.3V to VA + 0.3V 3
Input Current at Any Pin -10 10 mA 3
Package Input Current -20 20 mA 3
ESD Susceptibility Human Body Model 2500 V 100 pF through 1.5 kΩ 3
ESD Susceptibility Machine Model 250 V 220 pF through zero ohms 3
Junction Temperature TJ 150 °C 3
Storage Temperature Tstg -65 150 °C 3
Operating Temperature TA -40 105 °C 3
VA Supply Voltage VA 2.7 5.25 V 3
VD Supply Voltage VD 2.7 V +2.7V to VA 3
Digital Input Voltage 0 V 0V to VA 3
Analog Input Voltage 0 V 0V to VA 3
Junction-to-Ambient Thermal Resistance θJA 96 °C/W 16-lead TSSOP on 4-layer, 2 oz. PCB 3

CAD (KiCad official)

  • Symbol: ADC088S022CIMTX
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: adc088s022cimtx-etched.step / adc088s022cimtx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adc088s022cimtx.step / adc088s022cimtx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 62f86bcab479a83d, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF