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ADC08060CIMTX

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Texas Instruments Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADC08060CIMTX

Texas Instruments · Analog To Digital Converters (ADCs) · TSSOP-24

ADC08060CIMTX from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VA power_in Positive analog supply pin, connect to a clean, quiet +3V source and bypass with a 0.1 µF ceramic capacitor for each VA pin plus one 10 µF capacitor.
2 AGND power_in Ground return for the analog supply.
3 VRT input Top of the reference ladder, nominal range 1.0V to VA; together with VRB it defines the VIN conversion range and should be bypassed well.
4 VA power_in Positive analog supply pin, connect to a clean, quiet +3V source and bypass with a 0.1 µF ceramic capacitor for each VA pin plus one 10 µF capacitor.
5 AGND power_in Ground return for the analog supply.
6 VIN power_in Analog signal input with a conversion range of VRB to VRT.
7 VIN GND power_in Reference ground for the single-ended analog input VIN.
8 AGND power_in Ground return for the analog supply.
9 VRM passive Mid-point of the reference ladder, to be bypassed to a clean, quiet point in the analog ground plane with a 0.1 µF capacitor.
10 VRB input Bottom of the reference ladder, nominal range 0.0V to (VRT - 1.0V); together with VRT it defines the VIN conversion range and should be bypassed well.
11 AGND power_in Ground return for the analog supply.
12 VA power_in Positive analog supply pin, connect to a clean, quiet +3V source and bypass with a 0.1 µF ceramic capacitor for each VA pin plus one 10 µF capacitor.
13 D0 output Digital conversion data output, LSB; valid data is output just after the rising edge of the CLK input.
14 D1 output Digital conversion data output; valid data is output just after the rising edge of the CLK input.
15 D2 output Digital conversion data output; valid data is output just after the rising edge of the CLK input.
16 D3 output Digital conversion data output; valid data is output just after the rising edge of the CLK input.
17 DR GND power_in Ground return for the output driver supply.
18 DR VD power_in Power supply for the output drivers (+2.4V to VA); decouple well from VA if connected to it.
19 D4 output Digital conversion data output; valid data is output just after the rising edge of the CLK input.
20 D5 output Digital conversion data output; valid data is output just after the rising edge of the CLK input.
21 D6 output Digital conversion data output; valid data is output just after the rising edge of the CLK input.
22 D7 output Digital conversion data output, MSB; valid data is output just after the rising edge of the CLK input.
23 PD input Power Down input; when high the converter is in Power Down mode and the data outputs hold the last conversion result.
24 CLK input CMOS/TTL compatible digital clock input; VIN is sampled on the falling edge of CLK.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Data Converters
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (absolute max) VA 3.8 V 4
Driver Supply Voltage (absolute max) DR VD 3.8 V VA + 0.3V printed; VA max 3.8V 4
Input Current at Any Pin -25 25 mA 4
Package Input Current -50 50 mA 4
Storage Temperature -65 150 °C 4
Soldering Temperature, Infrared 235 °C 10 seconds 4
ESD Human Body Model 2500 V 4
ESD Machine Model 250 V 4
Operating Temperature Range TA -40 85 °C 4
Supply Voltage VA 2.7 3.6 V 4
Driver Supply Voltage DR VD 2.4 V +2.4V to VA 4
Ground Difference /GND - DR GND/ 0 300 mV 4
Upper Reference Voltage VRT 1 V 1.0V to (VA + 0.1V) 4
Lower Reference Voltage VRB 0 V 0V to (VRT − 1.0V) 4
Integral Non-Linearity INL -1.3 0.5 1.3 LSB VA = DR VD = +3.0V, VRT = +1.9V, VRB = 0.3V, fCLK = 60 MHz 5
Differential Non-Linearity DNL -0.9 0.4 1 LSB 5
Missing Codes 0 5
Full Scale Error FSE -28 18 28 mV 5
Zero Scale Offset Error ZSE -35 26 35 mV 5
VIN Input Voltage VIN 1.6 V VRB (min) to VRT (max) 5
Reference Ladder Resistance RREF 150 220 300 Ω VRT to VRB 5
Reference Ladder Current IREF 5.3 7.3 10.6 mA 5
Reference Delta VRT - VRB 1 1.6 2.3 V 5
Logical High Input Voltage VIH 2 V DR VD = VA = 3.3V 6
Logical Low Input Voltage VIL 0.8 V DR VD = VA = 2.7V 6
High Level Output Voltage VOH 2.4 2.6 V VA = DR VD = 2.7V, IOH = −400 µA 6
Low Level Output Voltage VOL 0.4 0.5 V VA = DR VD = 2.7V, IOL = 1.0 mA 6
Effective Number of Bits ENOB 7.1 7.6 Bits fIN = 10 MHz, VIN = −0.25 dBFS 6
Signal-to-Noise & Distortion SINAD 44.5 47 dB fIN = 10 MHz, VIN = −0.25 dBFS 6
Signal-to-Noise Ratio SNR 44.6 47 dB fIN = 10 MHz, VIN = −0.25 dBFS 6
Analog Supply Current IA 25 31 mA DC Input 7
Output Driver Supply Current DR ID 0.3 1 mA DC Input 7
Total Operating Current IA + DRID 25.3 32 mA DC Input 7
Power Consumption PC 76 96 mW DC Input 7
Maximum Conversion Rate fC1 60 70 MHz 7
Minimum Clock Low Time tCL 6.7 ns 7
Minimum Clock High Time tCH 6.7 ns 7
Output Delay tOD 8.2 12 ns CLK Rise to Data Valid 7

CAD (KiCad official)

  • Symbol: ADC08060CIMTX
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: adc08060cimtx-etched.step / adc08060cimtx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adc08060cimtx.step / adc08060cimtx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 1b175bf96d5de90b, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF