component
ADC0804LCWM
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADCs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "adc0804lcwm",
"title": "ADC0804LCWM",
"brief": "Texas Instruments Analog To Digital Converters (ADCs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
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"component": {
"mpn": "ADC0804LCWM",
"manufacturer": "Texas Instruments",
"package": "SOIC-20-300mil",
"pin_count": 20,
"category": "ADC/DAC/Data Conversion",
"subcategory": "Analog To Digital Converters (ADCs)",
"datasheet": "https://www.ti.com/cn/lit/gpn/adc0802-n",
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"distributor_links": {
"lcsc": "C701068",
"mouser": "926-ADC0804LCWM"
},
"distributor_check": {
"checked_at": "2026-10-09T23:54:32Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "deferred",
"error": "shared DigiKey quota guard: 514 calls left today"
},
"mouser": {
"pn": "926-ADC0804LCWM",
"status": "found",
"lifecycle": "Obsolete"
}
},
"pins": [
{
"number": "1",
"name": "CS",
"type": "input",
"description": "Chip select input; the converter starts when CS and WR are simultaneously low, and CS must be low together with RD to read data."
},
{
"number": "2",
"name": "RD",
"type": "input",
"description": "Read input; when CS and RD are both low, the INTR flip-flop is reset and the tri-state output latches are enabled onto DB7 to DB0."
},
{
"number": "3",
"name": "WR",
"type": "input",
"description": "Write input; a high-to-low transition resets the SAR and shift register, and an external WR pulse is required during the first power-up cycle to ensure start-up."
},
{
"number": "4",
"name": "CLK IN",
"type": "input",
"description": "External clock input, or it can be used with the internal clock generator and external RC elements on CLK R (pin 19)."
},
{
"number": "5",
"name": "INTR",
"type": "output",
"description": "Interrupt request output; it makes a high-to-low transition to signal end of conversion, and it is driven through an inverting buffer."
},
{
"number": "6",
"name": "VIN(+)",
"type": "power_in",
"description": "Non-inverting differential analog input, which gives good common-mode rejection and allows offsetting the analog zero-input voltage value together with VIN(-)."
},
{
"number": "7",
"name": "VIN(-)",
"type": "power_in",
"description": "Inverting differential analog input, used together with VIN(+) to provide differential analog voltage input with common-mode rejection and analog zero offset."
},
{
"number": "8",
"name": "A GND",
"type": "power_in",
"description": "Analog ground pin; a single-point analog ground separate from the logic ground should be used, with VREF/2 and analog input filter capacitors returned to this point."
},
{
"number": "9",
"name": "VREF/2",
"type": "power_in",
"description": "Reference voltage input for adjusting the full-scale reading, which allows encoding a smaller analog voltage span to the full 8 bits of resolution."
},
{
"number": "10",
"name": "D GND",
"type": "power_in",
"description": "Digital ground pin; the power supply bypass capacitor and the self-clocking capacitor should be returned to digital ground."
},
{
"number": "11",
"name": "DB7",
"type": "output",
"description": "Data bit 7 (MSB) of the tri-state output latches, enabled only when CS and RD are both low."
},
{
"number": "12",
"name": "DB6",
"type": "output",
"description": "Data bit 6 of the tri-state output latches, enabled only when CS and RD are both low."
},
{
"number": "13",
"name": "DB5",
"type": "output",
"description": "Data bit 5 of the tri-state output latches, enabled only when CS and RD are both low."
},
{
"number": "14",
"name": "DB4",
"type": "output",
"description": "Data bit 4 of the tri-state output latches, enabled only when CS and RD are both low."
},
{
"number": "15",
"name": "DB3",
"type": "output",
"description": "Data bit 3 of the tri-state output latches, enabled only when CS and RD are both low."
},
{
"number": "16",
"name": "DB2",
"type": "output",
"description": "Data bit 2 of the tri-state output latches, enabled only when CS and RD are both low."
},
{
"number": "17",
"name": "DB1",
"type": "output",
"description": "Data bit 1 of the tri-state output latches, enabled only when CS and RD are both low."
},
{
"number": "18",
"name": "DB0 (LSB)",
"type": "output",
"description": "Data bit 0 (LSB) of the tri-state output latches, enabled only when CS and RD are both low."
},
{
"number": "19",
"name": "CLK R",
"type": "input",
"description": "RC timing resistor input pin for the internal clock generator, used with an external RC pair to set the conversion clock."
},
{
"number": "20",
"name": "VCC (or VREF)",
"type": "power_in",
"description": "+5 V supply voltage, which also serves as the upper reference input to the resistor ladder."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pin assignments come from the shared pin table that covers both the NFH (PDIP) and DW (SOIC) 20-pin ; The datasheet does not state the '300 mil' width explicitly for the DW package in the text provided;; The datasheet lists DB7 to DB0 as 'O' (output). They are tri-state latched outputs, but the datashee",
"9/20 pins cited to the wrong page (name found elsewhere): ['8:A GND@p28', '10:D GND@p28', '11:DB7@p11', '12:DB6@p11']"
],
"pages_sent": 15,
"cost_usd": 0.0692,
"at": "2026-10-09T23:54:15"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/adc0802-n",
"pages": 58,
"sha256": "b6c1c25b7f733ef6",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 20,
"described": 20,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
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"footprint_binding": "identity",
"sha256": "59a10b341e6972b31d81802a048060326da627d8b92dcf4263064f4f62ec808e",
"checked": "2026-10-09",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
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"sha256": "e9f4161e1ec47a8a1b79d96dfb1d115d96699fd9f09d8f46c228900c600ef2d8",
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}
]
},
"metadata": {
"specs": {
"Manufacturer": "Texas Instruments",
"Package": "SOIC-20-300mil",
"Category": "ADC/DAC/Data Conversion",
"Pins": "20"
}
},
"variants": [],
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"discovery_pitch": "ADC0804LCWM (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
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"email": "[email protected]"
},
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