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ADC0804LCWM
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Texas Instruments Analog To Digital Converters (ADCs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADC0804LCWM
Texas Instruments · Analog To Digital Converters (ADCs) · SOIC-20-300mil
ADC0804LCWM from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip select input; the converter starts when CS and WR are simultaneously low, and CS must be low together with RD to read data. |
| 2 | RD | input | Read input; when CS and RD are both low, the INTR flip-flop is reset and the tri-state output latches are enabled onto DB7 to DB0. |
| 3 | WR | input | Write input; a high-to-low transition resets the SAR and shift register, and an external WR pulse is required during the first power-up cycle to ensure start-up. |
| 4 | CLK IN | input | External clock input, or it can be used with the internal clock generator and external RC elements on CLK R (pin 19). |
| 5 | INTR | output | Interrupt request output; it makes a high-to-low transition to signal end of conversion, and it is driven through an inverting buffer. |
| 6 | VIN(+) | power_in | Non-inverting differential analog input, which gives good common-mode rejection and allows offsetting the analog zero-input voltage value together with VIN(-). |
| 7 | VIN(-) | power_in | Inverting differential analog input, used together with VIN(+) to provide differential analog voltage input with common-mode rejection and analog zero offset. |
| 8 | A GND | power_in | Analog ground pin; a single-point analog ground separate from the logic ground should be used, with VREF/2 and analog input filter capacitors returned to this point. |
| 9 | VREF/2 | power_in | Reference voltage input for adjusting the full-scale reading, which allows encoding a smaller analog voltage span to the full 8 bits of resolution. |
| 10 | D GND | power_in | Digital ground pin; the power supply bypass capacitor and the self-clocking capacitor should be returned to digital ground. |
| 11 | DB7 | output | Data bit 7 (MSB) of the tri-state output latches, enabled only when CS and RD are both low. |
| 12 | DB6 | output | Data bit 6 of the tri-state output latches, enabled only when CS and RD are both low. |
| 13 | DB5 | output | Data bit 5 of the tri-state output latches, enabled only when CS and RD are both low. |
| 14 | DB4 | output | Data bit 4 of the tri-state output latches, enabled only when CS and RD are both low. |
| 15 | DB3 | output | Data bit 3 of the tri-state output latches, enabled only when CS and RD are both low. |
| 16 | DB2 | output | Data bit 2 of the tri-state output latches, enabled only when CS and RD are both low. |
| 17 | DB1 | output | Data bit 1 of the tri-state output latches, enabled only when CS and RD are both low. |
| 18 | DB0 (LSB) | output | Data bit 0 (LSB) of the tri-state output latches, enabled only when CS and RD are both low. |
| 19 | CLK R | input | RC timing resistor input pin for the internal clock generator, used with an external RC pair to set the conversion clock. |
| 20 | VCC (or VREF) | power_in | +5 V supply voltage, which also serves as the upper reference input to the resistor ladder. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | ADC/DAC/Data Conversion |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
ADC0804LCWM - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
adc0804lcwm-etched.step/adc0804lcwm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adc0804lcwm.step/adc0804lcwm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (58 pp, sha256
b6c1c25b7f733ef6, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADC0804LCWM
**Texas Instruments** · Analog To Digital Converters (ADCs) · SOIC-20-300mil
ADC0804LCWM from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip select input; the converter starts when CS and WR are simultaneously low, and CS must be low together with RD to read data. |
| 2 | RD | input | Read input; when CS and RD are both low, the INTR flip-flop is reset and the tri-state output latches are enabled onto DB7 to DB0. |
| 3 | WR | input | Write input; a high-to-low transition resets the SAR and shift register, and an external WR pulse is required during the first power-up cycle to ensure start-up. |
| 4 | CLK IN | input | External clock input, or it can be used with the internal clock generator and external RC elements on CLK R (pin 19). |
| 5 | INTR | output | Interrupt request output; it makes a high-to-low transition to signal end of conversion, and it is driven through an inverting buffer. |
| 6 | VIN(+) | power_in | Non-inverting differential analog input, which gives good common-mode rejection and allows offsetting the analog zero-input voltage value together with VIN(-). |
| 7 | VIN(-) | power_in | Inverting differential analog input, used together with VIN(+) to provide differential analog voltage input with common-mode rejection and analog zero offset. |
| 8 | A GND | power_in | Analog ground pin; a single-point analog ground separate from the logic ground should be used, with VREF/2 and analog input filter capacitors returned to this point. |
| 9 | VREF/2 | power_in | Reference voltage input for adjusting the full-scale reading, which allows encoding a smaller analog voltage span to the full 8 bits of resolution. |
| 10 | D GND | power_in | Digital ground pin; the power supply bypass capacitor and the self-clocking capacitor should be returned to digital ground. |
| 11 | DB7 | output | Data bit 7 (MSB) of the tri-state output latches, enabled only when CS and RD are both low. |
| 12 | DB6 | output | Data bit 6 of the tri-state output latches, enabled only when CS and RD are both low. |
| 13 | DB5 | output | Data bit 5 of the tri-state output latches, enabled only when CS and RD are both low. |
| 14 | DB4 | output | Data bit 4 of the tri-state output latches, enabled only when CS and RD are both low. |
| 15 | DB3 | output | Data bit 3 of the tri-state output latches, enabled only when CS and RD are both low. |
| 16 | DB2 | output | Data bit 2 of the tri-state output latches, enabled only when CS and RD are both low. |
| 17 | DB1 | output | Data bit 1 of the tri-state output latches, enabled only when CS and RD are both low. |
| 18 | DB0 (LSB) | output | Data bit 0 (LSB) of the tri-state output latches, enabled only when CS and RD are both low. |
| 19 | CLK R | input | RC timing resistor input pin for the internal clock generator, used with an external RC pair to set the conversion clock. |
| 20 | VCC (or VREF) | power_in | +5 V supply voltage, which also serves as the upper reference input to the resistor ladder. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | ADC/DAC/Data Conversion |
| Pins | 20 |
## CAD (KiCad official)
- Symbol: `ADC0804LCWM`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `adc0804lcwm-etched.step` / `adc0804lcwm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc0804lcwm.step` / `adc0804lcwm.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc0802-n) (58 pp, sha256 `b6c1c25b7f733ef6`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adc0804lcwm-datasheet.pdf)